Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 45 www.quickfiltertech.com
Run and Status Registers
30h CH1_PGA (Programmable Gain Amplifier Setting, FIR bypass)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 30h X X X fir_0_1_bypass X X pga_gain1 pga_gain0
pga_gain
* 00 = 1
01 = 2
10 = 4
11 = 8
Description: Sets the individual gain of the programmable gain amplifiers. The four settings are 1x 2x 4x or 8x the incoming signal.
fir_0_1_bypass
0 = In-circuit
*1 = Bypassed
Description: Bypasses the main FIR filter (filter 1).
31h CH1_STAT (Channel status) - AUTOSET
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 31h fir_outsat1 fir_outsat0 fir_inbuf_over1 fir_inbuf_over0 X adc_un adc_ov adc_oo
Once set these bits retain their value until reset by the user.
adc_oo
*0 = In range
1 = Out of range
Description: ADC out of range, high or low.
adc_ov
*0 = No overflow
1 = Overflow
Description: ADC out of range, high.
adc_un
*0 = No underflow
1 = Underflow
Description: ADC out of range, low.
fir_inbuf_over0
*0 = No overflow
1 = Overflow
Description: FIR, filter 0, input buffer overflow flag.
fir_inbuf_over1