JADE COMPUTER PRODUCTS PRESENTS Double D THE DOUBLE DENSITY DISK CONTROLLER HARDWARE MANUAL IOD-1200M REVISION C Copyright (C) 1980 Jade Computer Products 4901 Rosecrans Ave Hawthorne, California 90250 All Rights Reserved 1
JADE COMPUTER PRODUCTS 4901 W. ROSECRANS BLVD HAWTHORNE. CALIF 90250 SUBJECT: PRODUCT: REVISION: DATE: ENGINEERING CHANGE NOTICE # 1. DOUBLE D DISK CONTROLLER. BAND C REVISION BOARDS. AUGUST 4. 1980. IT HAS BEEN REPORTED THAT INSERTION OF THE DOUBLE D DISK CONTROLLER INTO OF SOME S100 SYSTEMS PREVENTS NORMAL OPERATION. USUALLY ON THESE SYSTEMS THE COMMON CHARACTERISTIC IS THAT THEY JUST WILL NOT OPERATE.
---------------------------------------------------------------SUBJECT: PRODUCT: REVISION: DATE: ENGINEERING CHANGE NOTICE # 3. DOUBLE D DISK CONTROLLER. BAND C REVISION BOARDS. AUGUST 4, 1980. THE DOUBLE D DISK CONTROLLER USES S-100 SIGNAL SWO*. CPUS SUCH AS SBC-I00 AND SBC-200 DO NOT GENERATE THESE SIGNALS AND THEREFORE PRESENT AN INTERFACE PROBLEM. THE FOLLOWING MODIFICATION HAS SOLVED THE PROBLEM WITH THE ABOVE MENTIONED BOARDS. 1.
---------------------------------------------------------------SUBJECT: ENGINEERING CHANGE NOTICE # 5B. PRODUCT: DOUBLE.D DISK CONTROLLER. REVISION: BAND C REVISION BOARDS. DATE: AUGUST 5. 1980. IMPORTANT NOTICE! BOARD MODIFICATION NEEDED ON REVISION C. THIS ECN PERTAINS TO THE USE OF THE DOUBLE D DISK CONTROLLER WITH JADE RELEASE # 2 OF CP/M 2.2. CONNECTOR J3 PIN #48 WAS DESIGNATED ILLEGAL PACK*. IT HAS BEEN REDEFINED AND IT IS NOW DESIGNATED TWO SIDED*. MANY SHUGART SA800/801. SIEMENS FD100-8.
---------------------------------------------------------------SUBJECT: PRODUCT: REVISION: DATE: ENGINEERING CHANGE NOTICE # 7. DOUBLE D DISK CONTROLLER. BAND C REVISION BOARDS. OCTOBER 6, 1980. NOTE: USE NATIONAL SEMICONDUCTOR 74LS123 ONE-SHOTS ON THE DOUBLE-D CONTROLLER BOARD. THE RESISTOR / CAPACITOR COMBINATIONS HAVE BEEN SELECTED TO PROVIDE PROPER PULSE PERIODS WHEN USED WITH THIS ONE-SHOT. DOUBLE D DISK CONTROLLER BOARDS (A&T AND KIT) ARE NOW SUPPLIED WITH NATIONAL SEMICONDUCTOR 74LS123S.
---------------------------------------------------------------SUBJECT: PRODUCT: REVISION: DATE: ENGINEERING CHANGE NOTICE # 9. DOUBLE D DISK CONTROLLER. BAND C REVISION BOARDS. OCTOBER 6. 1980. THE FOLLOWING JUMPER CONFIGURATION CAN BE USED WITH THE SHUGART SA800/801 MODEL DISK DRIVE. EACH DRIVE: A, DRIVE DRIVE DRIVE DRIVE DSI DS2 DS3 DS4 A: B: C: D: LAST DRIVE: Tl, B, C, Y, T2, T3, T4, T5, T6 HL, 800 THE L JUMPER IS SET DEPENDING ON THE -5V SUPPLY. CONSULT YOU SA800 MANUAL.
SHUGART SAS50/S51 ------- --------START WITH THE DISK DRIVE(S) SET TO FACTORY CONFIGURATION AS DESCRIBED IN THE SER1VE AND MAINTENANCE MANUAL. THEN PERFORM THE FOLLOWING ALTERATIONS TO THE DRIVE(S). 1. REMOVE THE ‘IW’ PLUG. THIS ALLOWS FOR LOWER WRITE CURRENT ON THE INSIDE TRACKS. 2. REMOVE THE ‘RS’ PLUG AND INSTALL THIS PLUG AT ‘RM’. THIS ALLOWS DRIVE READY TRUE WHEN DIRECTION (SIDE SELECT) IS SELECTING THE WRONG SIDE OF A SINGLE SIDED DISKETTE. 3.
---------------------------------------------------------------Subject: Product: Revision: Date: Engineering Change Notice # 10. Double D Disk Controller - QUME DATATRAK 8 DRIVES Band C boards. Release 2 software May 8, 1981. The following jumped options should be changed on the DATATRACK 8 disk drive for use with the DOUBLE D controller. QUME disk 1. Remove programmable shunt from P.C. board socket. Bend pins B, HL, and Z to prevent making contact. Replace shunt back into socket. 2.
TABLE OF CONTENTS DOUBLE D TABLE OF CONTENTS SECTION DESCRIPTION PAGE 1 1.1 1.2 1.3 INTRODUCTION SCOPE RELATED DOCUMENTATION DESCRIPTION 1 1 1 1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.
SECTION 1 INTRODUCTION SECTION 1 INTRODUCTION 1.1 SCOPE This manual contains the complete hardware description of the Jade Double Density Disk Controller. It provides the end user with construction and configuration procedures, and a functional description of the circuitry. 1.2 RELATED DOCUMENTATION Double D Software Manual P/N IOD-1201M FD 179X-01 Specifications Z80A-CPU Technical Manual 1.3 Jade Computer Products Western Digital Corp. Zilog, Inc.
SECTION 1 INTRODUCTION The powerful FD 1791-01 Formatter/Controller is used to encode and decode all data transfers to and from the disk drives. It also provides for the generation and checking of address marks, data marks, and the cyclic redundancy characters. Write precompensation can be selected under software control at three levels of intensity, providing flexible data recording.
SECTION 2 HARDWARE DESCRIPTION SECTION 2 HARDWARE DESCRIPTION 2.1 OVERVIEW The operational characteristics of the DOUBLE D are a function of both hardware and on-board software. The hardware provides the data paths, logic functions, and control signals necessary to implement such operations as head loading, drive selection, head positioning, and transferring data. It is the software that determines how the disk controller commands are interpreted and in what sequence controller events-take place.
SECTION 2 HARDWARE DESCRIPTION Figure 2-1. Memory Address Detection 2.3 PORT ADDRESS DETECTION S-100 address lines AO thru A7 are constantly monitored by the Port Address Detection circuit. This circuit is composed of IC 3F and part of 3E. See figure 2-2. Switches "PO" and "P1" are used to vary the selected port address from 40 thru 43 hex. An address match is indicated by BPA* (Bus - Port Addressed) being asserted. SWITCH P1 Close Close Open Open Figure 2-2.
SECTION 2 2.4 HARDWARE DESCRIPTION BUS CONTROL SIGNALS All Control Signals from the S100 bus are buffered by ICs 1H and 3K before internal use. These line receivers have schmitt trigger inputs typically offering 400 millivolts hysteresis. See Figure 2-3. In some older mainframes SLVCLR* is not implemented. For use in those systems POC* (pin 99) can be connected to SLVCLR* by 8 jumper (BRST* to POC*). 2.5 Figure 2-3.
SECTION 2 HARDWARE DESCRIPTION Z80A to test and reset ZINT* under software control. More on this later. ZINT also controls which 1K bank of internal memory is selected for bus access. When memory is switched to the S100 bus, the on-board Z80A has asserted SLVACK* and will not respond to an interrupt. At this time ZINT is used AS internal address bit 10. ZRST* is the reset line to the on-board Z80A.
SECTION 2 HARDWARE DESCRIPTION enable (RE* and WE*) timing for the FD 1791-01. A section of IC 1F and U-5 provide a MOS level clock driver for the Z80A as recommended by Zilog. Figure 2-6. Clock Circuit 2.8 PROCESSOR The on-board processor function is implemented with the Z80A. It was selected because of execution speed and compatibility with TTL logic families. The processor uses the on-board 2K static memory for program, stack, parameters, and for buffering single/multiple sectors of data.
SECTION 2 HARDWARE DESCRIPTION the on-board processor. The user should refer to FD 1791-01 specifications for a detailed description of this part. Access to the FD 1791-01 Status Port allows reading the disk interface signals. These are WRITE PROTECT*, READY*, INDEX*, TRACK-ZERO*, and SEEKCOMPLETE*. 2.10 DISK INTERFACE Disk Interface is provided by two gold-plated card edges at the top of the P.C. board. The 50 pin (J-3) card edge is intended for the 8" disk drives.
SECTION 2 HARDWARE DESCRIPTION BIT FUNCTION SECTION A3 A4 A5 A6 A7 Issue Step Pulse Clear Timer Reset Host Interrupt Initiate Timer Wait State Request 2.15 2.14 2.5 2.14 2.16 Table 2-4. 2.12 Address Bit Assignments BOARD LEVEL STATUS PORT The Board Level Status Port is a parallel input port to the onboard Z80A. It provides the processor with access to board signals that cannot be read from the FD 1791-01. These signals are listed and described in Table 2-5. See Figure 2-7 for circuit diagram.
SECTION 2 2.13 HARDWARE DESCRIPTION BOARD LEVEL COMMAND PORT The Board Level Command Port is a parallel output port of the on-board processor. It is used to select various parameters as listed in Table 2-6. See Figure 2-7 for circuit details. DATA BIT 0 1 2 3 4 5 6 7 SIGNAL NAME DSA DSB DSE SERO DDEN SID1 PCA PCB DESCRIPTION Drive select bit A 2**0.
SECTION 2 HARDWARE DESCRIPTION PCB PCA 0 0 1 1 Table 2-8. 2.14 PRECOMPENSATION 0 1 0 1 OFF 200 ns. 160 ns. 120 ns. Write Precompensation ON-BOARD TIMER The On-Board Timer provides both a motor control for 5" drives and a means for deselecting any drive if not used for a given period of time. The 1791-01 will unload the head of a drive if not used in 15 revolutions, but in some drives the stepper-motor will still Figure 2-8. consume power.
SECTION 2 2.16 HARDWARE DESCRIPTION WAIT STATE GENERATOR The Wait State Generator is used to synchronize the on-board processor to the Disk Controller when data is being transferred between the Double-D and la disk drive. The wait state is generated during the execution of an input instruction from the Board Level Status Port while address bit A7 is held high. The wait-state is held until the FD 1791-01 issues either a Data Request (DDRQ) or an interrupt (DINT). For circuit details refer to figure 2-10.
SECTION 2 2.19 HARDWARE DESCRIPTION MEMORY CONTROL The Memory Control Circuit is used to operate the on-board memory. When SLVACK* is high, the on-board Z80A is performing memory read and write operations. When the internal memory is present in the 8100 bus (SLVACK* low), the host processor may perform read and write operations. Refer to Figure 2-12 for circuit diagram. Figure 2-12. Memory Control Circuit S100 bus requests for read and write operations are decoded by IC 2K.
SECTION 2 HARDWARE DESCRIPTION IC 1K). During this strobe IWR* is held low,' indicating a write cycle for the 2114s. 2.20 WRITE PRECOMPENSATION The Write Precompensation circuit is used advance or retard the individual write data pulses. This is done to correct for a distortion called BIT SHIFT. This bit shift .is observed when reading a data stream from 1:1 diskette. Data pulses which are recorded close together, when read back, appear to spread apart.
SECTION 2 HARDWARE DESCRIPTION and provides enhanced data recovery margins in both single and double density. The loop is constructed of both digital and analog circuitry. Figure 2-14. Phase Detector and Filter The Voltage Controlled Oscillator (VCO) is a 741S123 with both sections configured to trigger each other. The control voltage is applied to the resistors R3 and R4/5. An increase in voltage corresponds to an increase in frequency.
SECTION 2 HARDWARE DESCRIPTION They tend to occur either a little early or late but the center of the spread in these pulses is centered in the window. Figure 2-15. VCO and Timing Generator The signal PDLL (Phase Detector Lead/Lag) divides the window into early and late sections. PDNF (Phase Detector Normal Frame) is always true in double density. Its complement PDIF (Phase Detector Illegal Frame) is used in single density only.
SECTION 2 HARDWARE DESCRIPTION in the next frame as the data pulse occurred that triggered the signal in the preceding frame. Figure 2-16 8 Inch MFM Operation All these signals are used by the Phase Comparator which adjusts VX. The comparator provides Pump Up and Pump Down signals, where the period of the pump pulse is the same as the deviation of the incoming data pulse from the window's center. See Figure 2-15.
SECTION 3 CONSTRUCTION SECTION 3 BOARD ASSEMBLY 3.1 INTRODUCTION If you have purchased the JADE DOUBLE D Disk Controller as a kit, we strongly urge you to read this section in its entirety before attempting to assemble the board. This board is intended for those people who have had some prior experience with digital electronics and circuit board assembly. If you do not, it is highly recommended that you find an experienced person to help you with the assembly of this board.
SECTION 3 CONSTRUCTION [ ] Install 18-pin sockets at 4C, 4DL, 4DR, and 4E. not solder yet. [ ] Install 20-pin sockets at 1F, 1H, 3K, 3L, 4F, 4H, 4J, 4K, 4L, and 4M. Do not solder yet. [ ] Install 40-pin sockets at 1J and 2D. Do not solder yet. [ ] Place the flat styrofoam cover you received with your kit box firmly against the component side of the board. Turn the board over, holding the flat styrofoam piece tightly against the board. Press the board down, forcing the sockets into the styrofoam.
SECTION 3 CONSTRUCTION Install the 3.3K ohm 8-pin SIP resistor at RP1 (2F). Be careful to align pin 1. [ ] Install the locations: 10K ohm trimmers [ ] R2 (1A) [ ] R5 (1B) at the following [ ] Be VERY CAREFUL in reading the resistor color codes as there are many different values used in this kit. If needed, use an ohmmeter! [ ] Install the 1.
SECTION 3 CONSTRUCTION [ ] R26 (4L) [ ] R52 (1A) [ ] Install the 33K resistor (Orange-Orange-Orange) R28 (1A-1B). [ ] Install the 13K resistor (Brown-Orange-Orange) at R30 (1A). [ ] Install the 22 ohm resistor (Red-Red-Black) AT R11 (1K-2K). [ ] Install the 240K resistor (Red-Yellow-Yellow) at R12 (1M). [ ] Install the 300 ohm resistor (Orange-Black-Brown) at R13 (1L-2M). [ ] Install (1A). the 22K [ ] Install the R31 (1A). 47K [ ] Install the 20K resistor (Red-Black-Orange) (2A).
SECTION 3 CONSTRUCTION (1L). [ ] Install the 0.
SECTION 3 CONSTRUCTION [ ] Install the 7805 regulator at U2 (3A-4A) using the heat sink and the #6 hardware. Use the needle-nose pliers to bend the 7805 leads before mounting it. Mount the regulator on the heat sink first, then solder. [ ] Install the 2N2907A transistors at U5 (2K-2L) and U8 (U1). Use two TO-18 spacers at this time. [ ] Install the 2N2222A transistor at U7 (U1). Use a TO18 spacer when mounting. [ ] Install the 79L12 regulator at U6 (4B). Align part as shown in silkscreen.
SECTION 3 CONSTRUCTION [ ] Install a jumper wire from "CLK" to "5" in the CLOCK SELECT BLOCK near ICs 2L-2M. [ ] For use with a 16 bit address bus install a jumper from "M" to "S" in the ADDRESS MODE JUMPER BLOCK. In this mode IC 4B is not needed. [ ] For use with a 24 bit address bus install a jumper from "M" to "E" in the ADDRESS MODE JUMPED BLOCK. In this mode IC 4B is required. [ ] Insert the LM358 at U4. Insert the 74LSOO IC at 1D. [ ] Insert the 74LS02 IC at 3C.
SECTION 3 CONSTRUCTION [ ] Inspect all inserted ICs for bent pins. [ ] Place DOUBLE D controller board in an extender board in an S100 mainframe. Open all switches in S1. Turn power switch on. [ ] Adjust trimmer R5 for a 2.0 MHz clock signal at IC 1B pin 12. (1.0 MHz for 5" configuration) [ ] Turn power switch off. Connect disk interface cable from controller to the disk drive. Observe pin 1 indications. Turn power switch on.
APPENDIX A COMPONENT LAYOUT AND FOIL PATTERNS 27
APPENDIX A COMPONENT LAYOUT AND FOIL PATTERNS 28
APPENDIX A COMPONENT LAYOUT AND FOIL PATTERNS 29
APPENDIX A COMPONENT LAYOUT AND FOIL PATTERNS 30
APPENDIX A COMPONENT LAYOUT AND FOIL PATTERNS 31
APPENDIX B PARTS LIST APPENDIX B PARTS LIST RESISTORS R1-8" 5" R2 R3-8" 5" R4-8" 5" R5 R6-8" 5" R7 RS R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 LOCATION-IC 10K 24K 10K BOURNS 1SK 39K 15K 36K 10K BOURNS 6.2K 8.2k 10K 4.7K 7.5K 30K 22 OHM 240K 300 OHM 4.7K 7.5K 10K 1.OK 10K 1.OK 27K 1.OK 4.7K 4.7K 4.7K 4.7K 5.1K 4.
APPENDIX B PARTS LIST R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 RP1 27K 4.7K 4.7K 470K 390K 2.4K 4.3K 4.3K 150 OHM 2.0K 120 OHM 82K 1.2K 220 OHM 5.1 K 2.7K 15 OHM 3.3K 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 5% 5% 5% 5% 5% 5% 5% 5% 3 WATT 8 PIN SIP 10% (1E) BOURNS 4116R-151 16 PIN 15 RESISTOR 150 OHMS, OR EQV.
APPENDIX B PARTS LIST CAPACITORS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 LOCATIONS 10 PF 5% MICA 25 PF 5% MICA 0.1 UF MONOLYTHIC 25 P-F 5% MICA 0.1 UF MONOLYTHIC 200 PF 5% MICA 25 PF 5% MICA 6.8 UF 35V DIPPED TANT. 200 PF 5% MICA 25 PF 5% MICA 0.1 UF MONOLYTHIC 0.1 UF MONOLYTHIC 0.1 UF MONOLYTHIC 25 PF. 5% MICA 200 PF 5% MICA 47 UF 6.3V DIPPED TANT. 0.1 UF MONOLYTHIC 200 PF 5% MICA 0.
APPENDIX B PARTS LIST DIGITAL CIRCUITS (1A) (1B) (1C) (1D) 74LS123 74LS123 74LS113 74LSOO (2A) (2B) (2C) (2D) 74LS123 74L821 74LS20 Z80A (1E) (1F) (1H) (1J) (1K) (1L) (1M) RES-PK 74LS240 74LS244 1791-01 7425 74LS04 7406 (2E) 74LS10 (2F) 74LS04 (2H) 7406 (0L) 74LS123 (0M) 74LS123 (2K) 7425 (2L) 74LS74 (2M) 74LS93 (3A) 74LS113 (3B) 74LS32 (3C) 74L802 (3E) (3F) (3H) (3J) (3K) (3L) (3M) ANAL0G CIRCUITS (U1) (U2) (U3) (U4) (U5) (U6) (U7) (U8) 78M12 (TO-5) 7805 (TO-220) *DELEATED* LM358 (8-PIN DI
APPENDIX C INTERNAL SIGNAL DEFINITIONS APPENDIX C INTERNAL SIGNAL DEFINITIONS BCPS BDBIN BDI* BLSTB BMA* BMA BMEMR BR* BPWR BSINP BSOUT BSWO BOARD - CONTROL PORT STROBE BUS - DATA BUS IN BOARD - DATA IN BOARD - FUNCTION STROBE BOARD - MEMORY ADDRESSFD BOARD - POR_ ADDRESSED BUS - MEMORY READ BOARD - RESET BUS - PROCESSOR WRITE BUS - STATUS INPUT BUS STATUS OUTPUT BUS STATUS WRITE OUT CHNG* DISK CHANGED DCLK DCRE* DCWE* DDEN DDIN* DDRQ DINT DSA DSB DSE 1791-01 CLOCK 1791-01 READ ENABLE 1791-01 WRITE E
APPENDIX C INTERNAL SIGNAL DEFINITIONS RCLK 1791-01 READ WINDOW SA11 SA12 SERI SERO SID1 SLVACK* SLVREQ* ADDRESS SWITCH M11 ADDRESS SWITCH M12 TTL LEVEL OF EIA IN TTL LEVEL OF EIA OUT SIDE 1 SELECT MEM TRANSFER ACK MEM TRANSFER REQ TOFF TST* TIMER OFF TEST PLL VFOE* VPC VX PHASE LOCK LOOP ENABLE PRECOMP INTENSITY LOOP OSC VOLTAGE WDNC WDPC WRITE DATA NOT COMPENSATED WRITE DATA PRECOMPENSATED ZCLK ZHLD* ZINT* ZNMI* ZRST* Z80A Z80A Z80A Z80A Z80A CLOCK WAIT REQUEST INTERRUPT REQ N.M.
