Technical information
TECHNICAL INFORMATION
Address Decoding Scheme
The Address Decoder logic consists
of
Z43,
Z40, Z39 and one
inverter from Z32.
Z40 is a dual 2-line
to
4-line demultiplexer. One half
of
this package
selects 16K increments
of
RAM. The input signals
to
this section are
MRAS*,
Al4
and
AIS.
MRAS* serves as a valid memory address
signal; a logical
f/J
indicates
that
the
addresses have stabilized. Table 1
summarizes
the
I/O combinations.
INPUTS
OUTPUTS
Z40
Z40
Z40
Z40
Address Range
MRAS'
A15
A14
Pin 4 Pin 5 Pin 6 Pin 7 Selected
1
X X 1 1
1 1
None
\1
0 0 0
1
1 1
0000-3FFF
0
0
1
1
0
1 1
4000-7FFF
0
1
0
1 1
0
1
8000-BFFF
0
1
1 1 1
1
0
C000FFFF
Note:
In the Table, X
~
Don't
care.
Table 1.
Pins 6 and 7 select
the
32K and 48K rows
of
dynamic RAM,
respectively. Pin 4 is looped back to
the
second
half
of
Z40. There, it
is
combined with
the
output
of
NAND gate Z43
to
give a logical 0
on
Pin 12 when
All,
A14,
AIS
and MRAS* are logical 0and AS, A6,
A7, A8, A9,
Al
0,
A12 and A
13
are logical 1. Pin 12 is logical 1 at all
other
times. Pin S
is
not
used.
It
is
shown in Table 1 only for
continuity
of
the
I/O combinations.
The signal from Pin
12
of
Z40
is
combined with A2, A3,
WR
* and
inverted RD* to produce
the
signals shown in Table 2.
INPUT
OUTPUT
240
239 239
239 239
239
239
239
239
SIGNAL SIGNAL
PIN
12
RD'
WR"
A3 A2
PIN 7
PIN 6
PIN 5 PIN 4 PIN 9
PIN 10
PIN
11
PIN 12
GENERATED
TO
1
X
X X X
1 1 1 1 1
1 1
1 NONE
-
0 0
1 0 0
0
1
1
1 1
1 1
1
37E0 READ
INTERRUPT
LOGIC
0 0
1
0
1
1
0
1
1 1
1 1 1
37E4 READ
-
0 0
1 1
0
1 1
0
1 1
1 1 1
37E8
READ
PRINTER LOGIC
0 0
1 1 1
1
1 1
0
1
1
1 1
37EC READ FLOPPY
DISK
CONTROLLER
0
1
0
0 0 1 1
1 1
0
1
1 1
37E0 WRITE
DRIVE
SELECT
0
1
0 0
1 1 1 1 1
1
0
1 1
CSW
CASSETTE
RELAY
0
1
0
1
0 1
1 1 1 1
1
0
1 37E8 WRITE
PRINTER LOGIC
0
1
0
1 1
1
1
1 1 1 1 1 0
37EC WRITE FLOPPY DISK
CONTROLLER
NOTE:
X =
Don't
Care
Table 2.
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