PROMENTUM® COMPUTE PROCESSING MODULE REFERENCE ATCA-4500 ATCA-4550 ATCA-4555 www.radisys.
Release history Version -0000 -0001 -0002 -0003 Date August 2009 August 2010 October 2010 December 2010 -0004 March 2011 -0005 June 2011 Description First edition. Second edition. New features and modifications. Third edition. Added ATCA-4555; revised Out of Service LED description. Fourth edition. Shielded serial/Ethernet cables required; updated reset sources list in Table 14; revised +1.5V DDR3 and +0.75V DDR3 threshold values. Fifth edition.
TABLE OF CONTENTS Preface................................................................................................................................................. 7 About this manual........................................................................................................................................7 What’s new in this manual ...........................................................................................................................7 Notational conventions .........
Table of Contents Super I/O chip............................................................................................................................................39 TPM chip ...................................................................................................................................................39 SAS and SATA ..........................................................................................................................................
Table of Contents Appendix A: Specifications ............................................................................................................. 91 Environmental specifications .....................................................................................................................91 Safety specifications..................................................................................................................................92 Mechanical specifications ........................
Table of Contents 6
PREFACE About this manual This manual describes the Promentum® ATCA‐4500, ATCA‐4550, and ATCA‐4555 compute processing modules (CPM), which offer compliance with AdvancedTCA® (PICMG 3.0 Advanced Telecommunications Computing Architecture R2.0). The modules can be incorporated into high availability (HA) systems, such as the Promentum SYS‐6010, SYS‐6014, and SYS‐6016. Use this manual as a reference for the operation and maintenance of the ATCA‐4500, ATCA‐4550, and ATCA‐4555 CPM.
Title Preface Notational conventions This manual uses the following conventions BoldText ItalicText MonoText BoldMonoText ItalicMonoText Brackets [ ] Curly braces { } Vertical line | A keyword. File, function, and utility names. Screen text and syntax strings. A command to enter. Variable parameters. Command options. A grouped list of parameters. An “OR” in the syntax. Indicates a choice of parameters. All numbers are decimal unless otherwise stated.
Where to get more product information Title Where to get more product information Visit the RadiSys Web site at www.radisys.com for product information and other resources. Downloads (manuals, release notes, software) are available at www.radisys.com/downloads. Related manuals See the following resources for information on the CPM not described in this manual: • Installation and initial setup instructions.
Title Preface Standards information For information about the PCI Industrial Computer Manufacturers Group (PICMG) and the AdvancedTCA standard, consult the PICMG Web site at this URL: http://www.picmg.org For more information about IPMI and the IPMI standards, consult the Intel Web site at this URL: http://developer.intel.com/design/servers/ipmi For information about SCSI storage interfaces (i.e.
Related Documents Title PICMG 3.1 R1.0 Ethernet/Fibre Channel over PICMG 3.0, PICMG. PICMG HPM.1 R1.0 Hardware Platform Management IPM Controller Firmware Upgrade Specification, PCI Industrial Computer Manufacturers Group, May 4, 2007. Serial Attached SCSI‐2 (SAS‐2) Specification (T10/1760‐D Revision 15); ISO/IEC 14776‐ 152:200x, November 19, 2008. SR‐3580 Network Equipment—Building Systems (NEBS) Criteria Levels, Issue 2, Telcordia, January 2005. UL 60950‐1 Safety for Information Technology Equipment.
Title 12 Preface
PRODUCT OVERVIEW 1 The Promentum ATCA‐4500, ATCA‐4550, and ATCA‐4555 Compute Processing Modules (CPMs) are high‐performance general‐purpose computing modules that provide multi‐ core processing power and multiple data‐storage options within a single slot. The CPM is ideal for control plane and server functions for LTE wireless infrastructure, Deep Packet Inspection, IPTV, IP multimedia subsystems, and defense applications.
1 Product Overview Block diagram Figure 1 illustrates the CPM’s major functional blocks. Chapter 4, Components and Subsystems, on page 31 contains detailed information about how the CPM functions. Figure 1. CPM functional blocks Front I/O (2) USB 2.0 (1) RS-232 (RJ-45) (2) 10/100/1000 Ethernet (RJ-45) Reset Switch ATCA LEDs AMC.3 – SAS (Port 3) 0 8 ; AMC.3 – SAS/SATA (Port 2) AMC.2 - GbE (Ports 0, 1, 8, 9) ) 5 AMC.
Quad-core processor with integrated memory controller 1 Quad-core processor with integrated memory controller For central processing operations, the ATCA‐4500 uses the Intel® Xeon® 5500 series processor, and the ATCA‐4550 and ATCA‐4555 use the Intel Xeon 5600 series processor. For detailed information about the processor and memory controller, see Processor and memory controller on page 31.
1 Product Overview Hardware management The function and operation of the CPM hardware management subsystem is controlled by the Intelligent Platform Management Controller (IPMC). The IPMC manages these functions: • Local hardware sensors for the CPM and RTM. • Electronic keying support for Fabric interface, synchronization clocks, and update channels. • System event log (SEL) • Remote executable flash and microcontroller software upgrade support.
INSTALLING MEMORY MODULES 2 Supported DIMM combinations There are eight DIMM sockets (dual inline memory modules) on the CPM for installing VLP DDR3 registered ECC DIMMs. In Figure 2, the sockets are grouped into three channels. When installing DIMMs, begin by populating the channels that are farthest from the CPU. Balance DIMMs across the channels by populating slot 0 for each channel first, followed by slot 1, and then slot 2. The preferred memory configurations are listed in Table 1.
2 Installing Memory Modules Mismatched DIMM combinations and SEL error events A memory initialization error occurs if memory channels are not consistently populated from the lowest‐numbered slot to the highest‐numbered slot. Using Channel A as an example in Figure 2 on page 17, slot A0 should be populated first, then A1 and then A2. The error occurs if Channel A only has A0 populated and Channel B only has B1 populated.
Installing the memory cards 2 Installing the memory cards 1. Open the DIMM socket ejector latches by pushing them outward. See Figure 4. Figure 4. DIMM sockets Ejector latch DIMM socket 2. The DIMMs are keyed so they can be inserted in only one way. Hold the DIMM by the edges, align the slot (keyway) of the DIMM with the tab molded in the base of the socket, and push the card down firmly into the socket. The ejector latches close and the DIMM clicks into place when it is firmly seated. 3.
2 Installing Memory Modules Testing installed memory After the DIMMs are installed and the CPM is installed in the shelf, verify that the expected memory is available and the memory is valid by performing the following tests. Verifying DIMM operation Verify that the BIOS detects and enables all installed memory. The total memory size detected and enabled is reported in the main page of the BIOS setup menu.
Running a memory test 2 The following is an example of memtest output: Shell> memtest LOOP: Starting pass 1 START: PASSED: PASSED: PASSED: PASSED: END: Testing Memory Region 0x8000 ‐> 0x5FFFF 0x8000 ‐> 0x5FFFF Addressing Test (Fast) 0x8000 ‐> 0x5FFFF Data Test (Patterns) 0x8000 ‐> 0x5FFFF Addressing Test (Complex) 0x8000 ‐> 0x5FFFF Data Test (Walking Bits) Total Error Count (All Tests) = 0.
2 22 Installing Memory Modules
LEDS AND EXTERNAL INTERFACES 3 This chapter describes the external indicators, switches, and ports for the CPM. Front panel LEDs, buttons, and ports Figure 5.
3 LEDs and External Interfaces The CPM has a metal front panel that serves as an EMI/RFI barrier and provides access to front panel ports and PICMG 3.0 required functions.
Front panel LEDs, buttons, and ports 3 Figure 6.
3 LEDs and External Interfaces Front panel LEDs Table 2 describes the front panel status and activity LEDs. Table 2. Front panel LEDs Label LED ID Definition Color OOS LED 1 Out of service Amber or red a LED states Controlled by the IPMC or the user. b Default behavior: • Default LED color is set by the IPMC • Always OFF, except for the following situation: • Persistent blink when both active and backup IPMC application images are invalid or corrupted.
AMC bay 3 Serial RS-232 connector An external computer can be attached to the CPM by connecting a shielded RJ‐45 cable to the computer and the front panel RS‐232 serial port. A shielded cable is required to minimize the possibility of issues related to external electromagnetic interference (EMI). The pinout for the RS‐232 connector is shown in Table 40 on page 141.
3 LEDs and External Interfaces Backplane interfaces Backplane connector J23 is the ATCA data transport connector, which provides Zone 2 connections for two 10/100/1000BASE‐T Ethernet Base channels and two 10GBASE‐BX4 Ethernet Fabric channels. See 10‐gigabit Ethernet Fabric interface on page 41 for details about all supported Ethernet Fabric channel modes. For more information about the backplane connectors, refer to Backplane interfaces on page 142.
Rear transition module (RTM) interface 3 Rear transition module (RTM) interface The CPM includes the standard Zone 3 backplane interface to provide connectivity to an optional RTM, such as the ATCA‐5400. This interface consists of two connectors: J30 for common and maintenance signals, and J31 for SerDes (serialization/deserialization connectivity). For details, refer to Zone 3 J30 connector pinout and Zone 3 J31 connector pinout on page 146.
3 30 LEDs and External Interfaces
COMPONENTS AND SUBSYSTEMS 4 This chapter discusses the CPM’s major components and subsystems. Processor and memory controller The CPM supports various versions of the Intel Xeon 5500 and 5600 series processors. The processor has an integrated memory controller and two point‐to‐point Quickpath Interconnect (QPI) interfaces for I/O Hub (IOH) and CPU connectivity. The processor cores share an 8MB cache and support SSE2, SSE3 and SSE4 streaming SIMD (Single Instruction, Multiple Data) extensions.
4 Components and Subsystems The CPU includes a single digital thermal sensor (DTS) that continuously measures the temperature at each processing core and provides processor die temperature information that represents the worst case temperature for all cores. The DTS data represents the difference between the current die temperature and the temperature at which the ATM activates the thermal control circuitry. The IPMC accesses DTS information through the platform environmental control interface (PECI).
Quick path interconnect 4 2x refresh mode The CPU doubles the refresh rate to the memory channels to better preserve the data when the DRAM is operating at elevated temperatures. The DRAM components have two temperature limits: T32 and T64. T32 is the temperature limit for a 1x refresh rate. T64 is the upper DRAM temperature limit when operating in 2x refresh mode. When T64 is exceeded, an SMI (system manager interrupt) is generated because the DRAM is operating out of specification.
4 Components and Subsystems DDR3 SDRAM The CPM has 8 VLP DIMM sockets for registered DDR3 SDRAM modules. These DIMM sockets are grouped into three independent channels. Two of the channels (A and B) can hold up to three DIMMs, while the third channel (C) only holds up to two DIMMs: • Three DIMMs per channel (A and B) is only supported for single‐ and dual‐rank DIMMs running at 800 MHz. • At 1066 MHz, only two DIMMs per channel are allowed for single and dual‐rank.
Redundant user flash 4 Redundant user flash The CPM optionally includes two banks of user flash memory with up to 16 GB storage capacity for each bank. Each redundant flash bank can be used to store an operating system and application image, allowing it to function as a boot device. Each user flash consists of an embedded universal serial bus (eUSB) flash module. The eUSB flash memory has a small form factor, low power consumption, and fast access time. The I/O controller hub uses standard USB 2.
4 Components and Subsystems I/O hub to PCI Express devices The CPM includes an Intel 5520 chipset I/O hub (IOH) that provides the bridge between the PCI Express (PCIe) devices in the system and the CPU QPI interface. The IOH provides 36 PCIe ports capable of Gen1 (2.5 GT/s) and Gen2 (5 GT/s) speeds. Table 5 shows the PCI Express port mapping. Table 5.
USB controller 4 USB controller The ICH contains two universal host controller interface (UHCI) controllers and two enhanced controller host interface (EHCI) controllers that share the same set of pins. Each pair of controllers provides up to twelve USB 1.1 or USB 2.0 ports. Each EHCI port allows data transfers up to 480 Mb/s and reports over‐current status back to the ICH. The CPM provides the five ports listed in Table 6 when configured for EHCI (USB 2.0): Table 6. USB 2.
4 Components and Subsystems Real-time clock The ICH includes an integrated real‐time clock (RTC) that keeps track of the time of day and date. The RTC circuitry includes 256 bytes of capacitor‐backed CMOS RAM. The RTC is derived from a 32.768KHz crystal with the following specifications: • Frequency tolerance @ 25°C: ± 20 ppm • Frequency stability: maximum of ‐0.
Super I/O chip 4 The ICH SMBus consists of a transmit data path and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The RTC clocks the ICH SMBus controller logic. The host controller’s programming model has two segments: a PCI configuration and a system I/O mapping. All static configurations, such as the I/O base address, are configured via the PCI configuration space.
4 Components and Subsystems Figure 7. SAS/SATA multiplexer connections Intel ICH10R SATA SATA Port 0 Port 1 AMC Bay (SAS / SATA HDD) Multiplexer SAS/SATA Port B Port 2 Port 3 Port A SAS Zone 3 Connector J30 SATA SAS/SATA SATA 0 SAS 1 SAS 0 Ethernet controllers and interfaces Gigabit Ethernet interfaces The CPM uses two dual gigabit Ethernet controllers (Intel 82576EB devices) to provide four GbE ports.
10-gigabit Ethernet Fabric interface 4 Base Interface The Base controller is configured for MDI (copper), providing 1000Base‐T, 100‐Base‐TX, and 10Base‐T support. The Base controller is connected to the BASE 1 and BASE 2 backplane ports, and the controller is connected with a x4 link to PCIe port 3 on the I/O hub. The EEPROM for the Base controller enables pass‐through mode via the SMBus, which allows the IPMC to implement serial‐over‐LAN on either base port.
4 Components and Subsystems Depending on the interface E‐Keying, Fabric channel 1 is configured as one of these options: • A 10GBase‐BX4 (or KX4) connected to Port 0 of the 10‐GbE controller • Three 1000Base‐BX (or KX) links. One link is connected to Port 0 of the 10‐GbE controller, and the two remaining links are connected to AMC Ports 0 and 8.
10-gigabit Ethernet Fabric interface 4 Figure 8.
4 Components and Subsystems AMC bay The CPM supports one Advanced Mezzanine Card (AMC) bay that is compliant with the AMC.0, AMC.1 (PCI Express), AMC.2 (Ethernet), and AMC.3 (Storage) PICMG specifications. The bay supports mid‐size modules and the RadiSys HDD‐AMC. The bay can provide up to the AMC.0 maximum of 80W, but the total power consumption allowed is 40W. The AMC bay has basic and extended connector sections.
AMC bay 4 The CPM’s IPMC provides intelligent platform management (IPM) connectivity between the backplane IPMB and the AMC’s local IPMB (IPMB‐L). Depending on the software involved, the AMC bay may be addressed in any of the following ways: PICMG 3.0 commands BIOS setup screens AMC.0 site number IPMB-L address AMC bay FRU 1 Slot 1 Site 5 0x7A The Shelf Manager refers to the AMC as bay 5, corresponding to the AMC.0 site number.
4 Components and Subsystems Table 8. AMC port interfaces (continued) Identity Extended options Fabric port 15 Function Port 15 of the AMC bay connects through the Zone 3 J30 connector to the RTM. These interconnections are to provide an I2C bus from the AMC module to the RTM for SFP and LED control. They also provide a serial port for RTM access to the AMC for debug. Per the AMC.0 specification, AMC modules are required to power up with their ports disabled if the signal levels used are non-LVDS.
Update channel connections to the AMC bay 4 The connections to Port 13 of each AMC bay are used for single‐ended general‐purpose I/ O (GPIO) signals. The signals on Port 13 power up disabled on both the AMC and the CPM, and are E‐Keyed. The E‐Keying function is provided by the IPMC on the CPM and the MMC on the AMC modules. Each controls the enable pins of their respective buffers with GPO pins. If an AMC module chooses to use Port 13, it must drive GPO outputs on the AMC‐side TX+ and TX‐ pins.
4 Components and Subsystems Intelligent Platform Management Controller The Intelligent Platform Management Controller (IPMC) monitors the health of the system and manages the CPM hardware by controlling power to the CPM payload, managing the sensors, using E‐Keys to enable ports, performing CPM resets, and executing IPMI commands. The IPMC consists of a microcontroller (a Renesas H8S/2166 device), an IPMC FPGA, and nonvolatile RAM.
HARDWARE MANAGEMENT 5 The hardware management subsystem includes the Intelligent Platform Management Controller (IPMC), the managed sensors, and the communication interfaces to external entities such as the Shelf Manager. The IPMC controls the hardware management subsystem by enabling payload power and ports, detecting component hardware states, initiating resets, and monitoring managed sensors. The CPM’s hardware management system complies with the Intelligent Platform Management Interface (IPMI) 1.
5 Hardware Management IPMC description The hardware management system of the CPM is controlled by an IPMC, which comprises a microcontroller, an IPMC FPGA, and EEPROMs for IPMC data storage.
IPMC FPGA 5 IPMC FPGA The IPMC FPGA consists of a Lattice LFXP6CF256I‐3 FPGA that is used to provide General Purpose I/O (GPIO) expansion for the IPMC. General purpose outputs (GPOs) from the IPMC FPGA are configured and reserved for power and reset controls on the CPM. When executing E‐Key logic, the IPMC uses the IPMC FPGA to connect I2C bus 3 to the multiplexer (see E‐Key control of interfaces on page 59). The FPGA also contains the IPMC’s hardware watchdog (see IPMC watchdog).
5 Hardware Management Redundant firmware images The H8 microcontroller firmware image is composed of a single boot image and dual redundant application images, all physically stored in the single internal flash for the H8. On reset or boot‐up of the H8, the boot image reads the Serial EEPROM of the IPMC entity to determine which H8 bank is the active bank. Next, the boot image validates the active and backup application images.
Summary of IPMC controls 5 Summary of IPMC controls The IPMC manages resets, power states, and IPMB isolation for the CPM and its AMC and RTM. The output actuators (defined in the PICMG 2.0 specification) are implemented as IPMC GPIO outputs controlled by the IPMI firmware. Note: Under normal running conditions, the IPMC controls the state of the GPIO outputs. However, the controls can be accessed for debug situations using the Set/Get Control State OEM IPMI commands.
5 Hardware Management RTM controls The IPMC manages the RTM controls listed in Table 12. Table 12. IPMC-managed RTM controls Control RTM Payload Power Enable (+12V) RTM Isolator RTM Payload Reset RTM_PCIE_PRES RTM_PCIE_BUTTON RTM Management Power (+3.3V) RTM PCIE CLK Enable Function RTM_+12 Power Enable: controls RTM 12V power RTM I2C Enable: isolates the RTM module from the CPM I2C Bus 5 RTM Bay MMC Reset (ENABLE*) Asserted for RTM with PCI Express capability when the AMC is ready to be activated.
CPM resets 5 CPM resets The CPM supports only cold and powergood resets. Any warm reset sources are converted to a cold reset by the legacy FPGA. Cold reset A cold reset is a total system board reset (except for the IPMI circuitry). All devices and registers are reset to their default state. After a cold reset, data in DRAM might be invalid due to the CPU memory controller discontinuing refresh cycles. Memory is then cleared during the system BIOS initialization.
5 Hardware Management Reset source monitor The RST_SRC inputs of the IPMC are used to monitor the various reset sources on the board. When one of the inputs is asserted, an interrupt is generated to the IPMC. The IPMC can then determine what action to take based on previous actions, such as watchdog, soft, or hard reset. In addition, the IPMC monitors resets triggered by the IPMC itself, such as the IPMI watchdog or CFD timeout. The IPMC reset sources are listed in Table 14. Table 14.
Watchdog timers 5 Watchdog timers The CPM provides four watchdog timers (see Table 15) to help prevent the board from entering an unrecoverable state. The IPMC and the IPMC FPGA provide the watchdog timers. Figure 12 illustrates when and how the CPM enables, resets, and disables watchdog timers. Figure 12.
5 Hardware Management IPMC watchdog The IPMC FPGA includes a hardware watchdog timer, referred to as Watchdog 2. This watchdog prevents IPMC hardware or firmware problems from impacting the ability of other modules installed in the chassis to use the IPMB buses. The IPMC watchdog is enabled by default and starts running as soon as power is present and the IPMC FPGA has loaded its internal flash image into its internal SRAM. The default timeout on power‐up is 10 seconds.
Hot swap of the CPM and managed FRUs 5 Hot swap of the CPM and managed FRUs The CPM and its managed FRUs are hot‐swap capable and meet the hot‐swap requirements defined in the PICMG 3.0 Revision 2.0 AdvancedTCA Base Specification. The Shelf Manager controls the hot‐swap process, and the IPMC enables and disables payload power to the managed FRUs (the AMC and the RTM) when instructed by the Shelf Manager.
5 Hardware Management Update channel 0 is considered the “fast path” update port and connects the AMC bay port 12 to the Zone 2 connector. It is E‐Keyed (enabled or disabled) through a set of differential buffers that are controlled by the IPMC. Update channel 4 is considered the “slow path” update port and connects the AMC bay port 13 to the Zone 2 connector. The “slow path” is E‐Keyed with single‐ended TTL‐level buffers.
E-Key control of interfaces 5 As an AMC carrier, the CPM IPMC works with the AMC’s module management controller (MMC) to match the ports on the AMC’s connector to the corresponding CPM ports. The IPMC or MMC can disable ports that are not compatible. Table 18 lists the entities that provide E‐Key control for each AMC port on the CPM. Table 18.
5 Hardware Management IPMI-over-LAN A remote management application can establish an IPMI‐over‐LAN session with the IPMC. The IPMC is remotely accessible through the front serial port (COM1), the rear serial port (COM2), and the Base Ethernet ports. The CPM implements IPMI‐over‐LAN using RMCP and RMCP+ as described in the IPMI 2.0 specification. The IPMI‐over‐LAN session can be used to enable the functionality described in Serial‐over‐LAN on page 65.
Configuring IPMI-over-LAN access 5 IPMI-over-LAN basic configuration steps From the Linux prompt: 1. Set the IP address for a Base interface channel or the front/rear Ethernet interface channel: rsys‐ipmitool ‐I lan ‐H ‐A none ‐t lan set ipaddr The ‐I option specifies the IPMI interface to use (lan), and the ‐A option specifies an authentication type to use during session activation (none). The other command options are defined in Step 2 on the previous page.
5 Hardware Management IPMI-over-LAN additional configuration steps If IPMI‐over‐LAN does not work after performing the basic steps: 1. Set the user privileges for both channels: rsys‐ipmitool ‐I lan ‐H ‐A none ‐t user priv 1 4 2 rsys‐ipmitool ‐I lan ‐H ‐A none ‐t user priv 2 4 2 2.
Serial-over-LAN 5 Serial-over-LAN Serial‐over‐LAN (SOL) is the specification of packet formats and protocols for transmitting serial data over a LAN using IPMI‐over‐LAN packets. SOL operation is conceptually straightforward. A remote management application can establish an IPMI‐over‐LAN session with the IPMC. Once the session is established, the remote console can request SOL session activation. The COMux CPLD contains the multiplexer functionality for routing COM port signals.
5 Hardware Management Figure 14. Serial-over-LAN – no cables attached I/O Controller Hub (ICH10R) IPMC Front RJ-45 No cable Rear RJ-45 Base Ethernet Controller (82576EB) Base Interface 2 Network COM1 CON_COM1=[0,1] No cable I2C Bus 4 OR COMux CPLD COM1 IPMC Snoop CON_COM1=0 IPMC Snoop CON_COM1=1 COM2 COM2 COM1 Super I/O Front/Rear Ethernet Controller (82576EB) Front/ Rear Ethernet Ports SOL is supported through the Base interface or the Front/Rear ports, but not both simultaneously.
Serial-over-LAN 5 Figure 16. Serial-over-LAN – cable installed for front only I/O Controller Hub (ICH10R) I2C Bus 4 IPMC Base Ethernet Controller (82576EB) Base Interface 2 Network COM1 CON_COM1=[0,1] Cable Front Connected RJ-45 COM1 OR COMux CPLD IPMC Snoop No Rear cable RJ-45 COM2 COM2 COM1 Front/Rear Ethernet Controller (82576EB) Front/ Rear Ethernet Ports SOL is supported through the Base interface or the Front/Rear ports, but not both simultaneously.
5 Hardware Management Table 20 summarizes the SOL serial port connections. Table 20.
Establishing a SOL session 5 Establishing a SOL session Prerequisite: This procedure assumes that the required setup for IPMI‐over‐LAN has been done once for this CPM. For details, see Configuring IPMI‐over‐LAN access on page 62. One-time SOL configuration steps Important: For these one‐time steps, use the RadiSys‐supplied rsys‐ipmitool utility. To configure retry settings from a remote computer: 1. Configure the retries to keep SOL sessions open for a Base, front, or rear interface IP address.
5 70 Hardware Management
SYSTEM BIOS 6 The system BIOS is based on AMIBIOS® from American MegaTrends and is adapted by RadiSys. The BIOS setup utility appearance resembles a legacy BIOS setup, but the CPM AMIBIOS firmware is compatible with an extensible firmware interface (EFI). The BIOS offers pre‐EFI initialization and a pre‐initialization shell, a driver execution environment, and boot services. BIOS setup menus The system BIOS contains a setup utility for modifying the system configuration.
6 System BIOS Table 21.
Command line utility for changing BIOS settings 6 Command line utility for changing BIOS settings Use the bioscli2 utility to view and change EFI BIOS settings through the Linux command line. The utility can also create a file containing the BIOS settings, which can be used to distribute the same settings to other CPM modules. For example, to list all valid online BIOS settings, enter: bioscli2 ‐l See BIOSCLI2 commands on page 167 for a list of bioscli2 commands.
6 System BIOS Creating a custom BIOS image The following procedures explain how to extract and restore a BIOS image that includes your custom settings. Extract the BIOS image 1. Ensure the BIOS image to be extracted has the preferred BIOS settings and those settings were saved using BIOS Setup. 2. Start the CPM and verify its operating system has the rsysbflash utility installed. If it is not installed, follow these steps: a. Locate the ATCA‐45xx‐.
Configuring the front or rear Ethernet ports 6 Configuring the front or rear Ethernet ports Front or rear Ethernet ports are configured in the BIOS settings. The default configuration is to use the front panel Ethernet ports, but the CPM can be configured to redirect the front Ethernet to the rear RTM Ethernet ports.
6 System BIOS BIOS event and error reporting The BIOS sends these events to the IPMC during BIOS start‐up, early POST tasks, and execution: • System events • Boot events • POST error events during early POST tasks The IPMC logs the events to its local SEL and forwards them to the system SEL. Correctable and uncorrectable memory error logging The Integrated Memory Controller (IMC) supports ECC to detect and correct memory errors whenever possible.
Correctable and uncorrectable memory error logging 6 5. A software‐maintained counter is incremented whenever a correctable memory error SMI occurs. It is a single counter for correctable memory error from all DIMMs. The software counter is maintained by the BIOS and is cleared when the system is booted. The SMI only occurs if the correctable error threshold is reached (the hardware counter).
6 System BIOS Accessing the SEL Messages in the SEL are viewed using the rsys‐ipmitool utility. For example, to view the system SEL from a system that has LAN connectivity to the active Shelf Manager: rsys‐ipmitool ‐I lan ‐H ‐A NONE ‐t 0x20 sel list Use the ‐h option to obtain help using the utility. To view the CPM’s local SEL, substitute the IPMB address of the CPM for the value 0x20 in the command above.
SEL event codes 6 Table 23.
6 System BIOS Table 23.
SEL event codes 6 Table 23.
6 System BIOS Table 23.
SEL event codes 6 Table 23.
6 System BIOS Table 23.
MAINTENANCE AND TROUBLESHOOTING 7 Field replaceable units (FRUs) The following CPM‐related items can be installed or replaced: • The CPM itself. For installation instructions, see the ATCA‐4500, ATCA‐4550, ATCA‐4555 Compute Processing Module Installation Guide. For removal instructions, see Removing and installing the CPM, RTM, or AMC. • The DIMMs. For placement information and installation and removal instructions, see Chapter 2, Installing Memory Modules, on page 17. • A compatible AMC.
7 Maintenance and Troubleshooting WARNING! • Never force open a locking ejector latch. The locking mechanism must be disengaged to release the latch or damage to the latch could occur. • Do not remove an AMC, CPM, or RTM before its hot-swap LED turns solid blue. Removing it prematurely can cause unpredictable results in other parts of the system. 5. When it is safe to remove the AMC or module, the hot‐swap LED stops blinking and remains on.
Overview of firmware updates 7 Important: If the CPM is installed in logical slot 1 (slot address 0x82) for a 2‐slot shelf, the CPM by default assumes the role as the active shelf manager module. This may not be the desired behavior if the shelf already has a shelf manager installed, such as a Switch and Control Module (SCM) or a Chassis Management Module (CMM). For more information on installing a CPM, see the ATCA‐4500, ATCA‐4550, ATCA‐4555 Compute Processing Module Installation Guide. 10.
7 Maintenance and Troubleshooting • By specifying the CPM’s Base interface IP address in the upgrade commands. This method is available when access to the IPMC has been configured as described in IPMI‐over‐LAN on page 62. Instructions for upgrading all necessary components are included in the ATCA‐45xx CPM Firmware and Software Upgrade Instructions, available from the RadiSys Web site. RPMs required for updates Before running any updates, you need to prepare the CPM by installing the latest OS RPMs.
General troubleshooting tips 7 General troubleshooting tips When the CPM does not perform as expected, look for symptoms that might clarify the cause. Performing the following actions can help diagnose the problem: • Check the state of the LEDs on the CPM and other modules in the platform, especially the power and out of service LEDs. • Check the events logged in the Shelf Manager’s system event log (SEL) or the CPM’s local SEL. For information on accessing the SEL, see Accessing the SEL on page 78.
7 Maintenance and Troubleshooting Table 25. Troubleshooting actions based on symptoms (continued) Symptom The CPM or another module overheats. Recommendation • Verify that a generic front panel is not installed in the shelf. Instead, empty slots must have air management filler panels designed for the shelf’s slots installed to properly maintain airflow and emissions. • Check temperatures at the air intake on the overheating module and at the platform’s air exhaust.
SPECIFICATIONS A Environmental specifications RadiSys does not provide environmental certification testing because any meaningful emissions agency certification must include the entire system. Thus, the CPM is designed and tested to pass the environmental specifications noted below, but is not certified. WARNING! This product contains static-sensitive components and should be handled with care. Failure to employ adequate anti-static measures can cause irreparable damage to components.
A Specifications Table 26. Environmental specifications (continued) Characteristic Shock (drop) Vibrationb Seismic State Unpacked Value 0 to < 10 kg = 100 mm drop Free fall, corners and edges Packaged (Unpalletized) 10 to < 25 kg = 75 mm drop 0 to < 10 kg = 750 mm drop Free fall, corners and edges Palletized Operating Transportation (packaged) 10 to < 25 kg = 600 mm drop 300 mm free fall drop 0.1g, 5 to 100 Hz and back, 0.1 octave/min sine sweepb 0.5g, 5 to 50 Hz and back, 0.
Electromagnetic compatibility (EMC) A Electromagnetic compatibility (EMC) The ESD, EMC, and Immunity specifications are measured with ambient temperature between 20C and 30C and relative humidity between 30% and 50%. Table 29.
A Specifications Power consumption Table 30. CPM power consumption Product CPM with SAS drive and RTM installed CPM with AMC and RTM installed Typical power consumption measured at 25° C 85 W 116 W Maximum power consumption measured at 55° C 163 W 185 W Table 31.
General assumptions A General assumptions • • • Component failure rates are constant. Board‐to‐system interconnects are included within estimates. Non‐electrical components (screws, mechanical latches, labels, covers, etc.) are not included in estimates. General notes • • Method I, Case I = Based on parts count. Equipment failure is estimated by totaling device failures rates and quantities used.
A 96 Specifications
IPMI COMMANDS AND MANAGED SENSORS B Supported IPMI commands Table 33 lists the supported IPMI commands. Table 33.
B IPMI Commands and Managed Sensors Table 33. Supported IPMI commands (continued) Message commands Set Event Receiver Get Event Receiver Platform Event (a.k.
Supported IPMI commands B Table 33.
B IPMI Commands and Managed Sensors OEM command descriptions Special commands are available to facilitate CPM-specific functionality. Descriptions of each command and their parameters are listed in this section. Restore Factory Defaults Restores the factory default configuration and threshold parameters for onboard sensors. No data byte is required.
OEM command descriptions B Set Control State (for debug only) Overrides the current firmware setting of the control pin. Use only for debug situations.
B IPMI Commands and Managed Sensors RTM Reset Button Instructs the H8 IPMI firmware to perform a cold reset. NetFn 0x2E Cmd 0x15 Data field Byte 1 Radisys IANA PEN0: F1h Byte 2 Radisys IANA PEN1: 10h Byte 3 Radisys IANA PEN2: 00h Byte 1 Completion code Byte 2 Radisys IANA PEN0: F1h Byte 3 Radisys IANA PEN1: 10h Byte 4 Radisys IANA PEN2: 00h Response field Set Payload Status Informs the H8 IPMI firmware about the current payload processor status.
OEM command descriptions Byte 6 B Status Byte 2 Bits 7:0 = Reserved Response field Byte 1 Completion code Byte 2 Radisys IANA PEN0: F1h Byte 3 Radisys IANA PEN1: 10h Byte 4 Radisys IANA PEN2: 00h Get Payload Status (debug only) Returns the H8 IPMI firmware acknowledgement of the payload processor status. The BIOS/OS uses this command to check if the IPMI firmware finished the internal processes for the x86 processor complex boot phase specified in a sent Set Payload status command.
B IPMI Commands and Managed Sensors Managed sensors On the CPM, the IPMC sensors monitor voltages, temperatures, control signals, and status events. For functional information, refer to IPMC description on page 50. The sensors are described in Table 35 on page 105. Types of sensors The CPM implements the following types of sensors. • Discrete — A discrete sensor can have up to 16 bitmapped states, with one state as true.
List of sensors B List of sensors Table 35 provides details about the sensors managed by the IPMC. All sensors generate events unless noted otherwise in the table footnotes. Note: The digital and discrete sensor readings reported by the active Shelf Manager may differ from the raw values reported in Table 35. 02h 03h 04h 05h PICMG Hot ATCA FRU swap event Hotswap 00h F0h Sensorspecific 6Fh 00h07h 06h 07h 00h 01h Per PICMG 3.0 spec Per PICMG 3.0 spec Per PICMG 3.0 spec Per PICMG 3.
B IPMI Commands and Managed Sensors Per PICMG 3.0 spec Per PICMG 3.0 spec 02h - 07h - 08h - M0 – FRU not installed M1 – FRU inactive M2 – FRU activation request M3 – FRU activation in progress M4 – FRU active M5 – FRU deactivation request M6 – FRU deactivation in progress M7 – Communication lost Firmware or software change detected with associated entity. Informational. Success or failure not implied.
List of sensors B SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35.
B IPMI Commands and Managed Sensors SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35. Managed sensors (continued) SPD DIMM B0 Temp 0Ah Temp 01h Threshold 01h 25 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.
List of sensors B SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35. Managed sensors (continued) SPD DIMM C1 Temp 0Eh Temp 01h Threshold 01h 25 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.2 01h IOH Die Temp 10h Temp 01h Threshold 01h 25 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.
B IPMI Commands and Managed Sensors SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35. Managed sensors (continued) Notes This sensor measures temperature in °C. The sensor monitors the ProcHot signal and, when it is asserted, reports a reading of 90.
List of sensors B SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35. Managed sensors (continued) +12V Threshold 19h Voltage 02h 01h 12.00 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.2 01h +5V Threshold 1Ah Voltage 02h 01h 5.00 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.
B IPMI Commands and Managed Sensors Standby Polling time (seconds) Readable value/offsets Event data Assert/Deassert events Normal reading Table 35. Managed sensors (continued) Threshold +1.8V CPU 1Fh Voltage 02h 01h 1.80 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.2 01h +1.8V BASE Threshold 20h Voltage 02h 01h 1.80 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.2 01h +1.8V FRONT Threshold 21h Voltage 02h 01h 1.80 R, T - - [u,l][nr,c,nc] As & De Analog A - 0.2 01h +1.
List of sensors B SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name Sensor number Table 35. Managed sensors (continued) Notes This sensor measures voltage in Volts. Default thresholds LNR LC LNC UNC UC UNR 0.00 0.90 0.96 1.28 1.34 1.37 This sensor measures voltage in volts. Default thresholds LNR LC LNC UNC UC UNR 0.00 0.90 0.95 1.05 1.
B IPMI Commands and Managed Sensors Flash bank 0 has been selected 00h - - 00h OEM Active Boot Flash 2Bh OEM EEh BMC Watchdog 114 Sensorspecific 6Fh SensorWatchdog 2 specific 6Fh 2Ch 23h 0 or 1 01h N/A 00h 01h 02h 03h 04h 07h 08h Flash bank 1 has been selected Timer expired, status only (no action, no interrupt) Payload Cold Reset Payload Power Down Payload Power Cycle Reserved Pre-Timer Interrupt As Yes A - 0.1 See OEM Active Boot Flash sensor (2Bh) 01h on page 123. As Yes A X 0.
B List of sensors ATCA Phys IPMB ATCA Physical IPMB-0 2Eh F1h ATCA Physical IPMB-L 2Fh OEM EBh Critical interrupt NMI 30h 13h Power +12V RTM Supply PwrFail4 31h 08h Power Supply +3.
B IPMI Commands and Managed Sensors IOH Therm Trip2 Temp 35h 01h IOH Therm Alert2 Temp 36h 01h DDR Therm Temp T642 37h 01h CPU CAT ERR2 AMC PwrFault RTM PwrFault AMC PCIe PwrEn RTM PCIe PwrEn 116 Processor 38h 07h Power Supply 39h 08h Power Supply 3Ah 08h Power Supply 3Bh 08h Power Supply 3Ch 08h SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Power Supply +3.
B List of sensors SDR type Event Standby Polling time (seconds) Byte 3 Rearm Event offset ED1 [3:0] Byte 2 Readable value/offsets Event data Assert/Deassert events Sensor type Event/ reading type Normal reading Sensor name ENET Link 0 (Ethernet link for FRONT/ REAR port) ENET Link 1 (Ethernet link for FRONT/ REAR port) ENET Link 2 (Ethernet link BASE port 0) ENET Link 3 (Ethernet link BASE port 1) ENET Link 4 (Ethernet link FABRIC port 0) ENET Link 5 (Ethernet link FABRIC port 1) Sensor numbe
B IPMI Commands and Managed Sensors 118 Sensor Specific 6Fh N/A FFh A X SDR type 05h Contains hex value from 0 to 100 decimal (00h to 64h), representing the % of the SEL filled at the time the event was generated. 00h is 0% full (SEL is empty), 64h is 100% SEL Almost Full full.
List of sensors B Critical Intr8 Critical Interrupt 46h 13h Sensor Specific 6Fh N/A N/A 00h - 01h - 05h 04h - 07h 04h 05h PCI bus number for failed device As - - - N/A 03h PCI SERR As - - - N/A 03h Event Event Data 3 (for both event offsets 0h, 1h): [7:6] – Rsvd.
B IPMI Commands and Managed Sensors Boot Error Boot Error8 48h 1Eh System Event8 Evn Receiver Addr9 120 System 49h Event 12h 4Ah OEM E9h N/A Readable value/offsets Assert/Deassert events System Firmware Error (POST Error) System Firmware Hang System Firmware Progress As - - - N/A 03h Event SDR type Event offset ED1 [3:0] Byte 2 Byte 3 See System Firmware 00h Progress sensor in 01h Table 23 on page 78 for details.
List of sensors B OEM HPM Event 4Bh OEM EFh Sensor Specific 6Fh N/A 00h 02h Currently executing application image # 01h – Bank 1 02h – Bank 2 Corrupted application image # 01h – Bank 1 Application Image 02h – Bank 2 Corruption SDR type 01h Bits 7:4 == Currently executing application image number 01h – Bank 1 02h – Bank 2 Bits 3:0 == Image number specified in non-volatile boot record (active) 01h – Bank 1 02h – Bank 2 Boot Failure Error Event Standby Polling time (seconds) Byte 3 00h Rearm E
B IPMI Commands and Managed Sensors 0 N/A 0 OEM HPI 4Fh OEM D6h OEM 70h N/A AMC sensor number range: From 0xA0 to 0xC7 RTM sensor number range: From 0xC8 to 0xEF 1 3 4 5 6 7 8 9 As - - - N/A 03h As - - - Only applicable if CPM is in IPMB Addr N/A 03h 0x82 and acts as shelf manager.
OEM sensor details B OEM sensor details This section provides details about the OEM managed sensors listed in Table 35 on page 105. OEM Payload Reset sensor (2Ah) The OEM Payload Reset sensor (managed sensor 42) indicates the cause of payload resets that occur during standard CPM operation. Each time a payload reset occurs, an event containing the cause of the reset is generated by the CPM. The logic for the reset sensor is located on the IPMC FPGA, where all reset sources are physically routed.
B IPMI Commands and Managed Sensors Table 37. OEM Active Boot Flash sensor event data format Event Data 3 Data Field The cause of reset.
Sensor alarm troubleshooting B IOH Die temperature sensor (10h) The Intel 5520 IOH provides an on-die temperature measurement which can be accessed via the on-die Thermal Sensor Fan-Speed Control Register (IOH TSFSC). This field contains the difference between the die temperature and the maximum permissible die temperature. The register has a resolution of 0.5° C. Hence, a value in the range of 0 to 127 refers to a temperature difference of 0 to 63.5° C lower than the maximum permissible die temperature.
B IPMI Commands and Managed Sensors Table 38. Sensor alarms and recommended actions (sheet 2 of 14) Number Name 07h SPD DIMM A0 Temp 08h 126 SPD DIMM A1 Temp Alarm level Minor temperature high Major temperature high Possible errors or faults Temperature over 72°C threshold. Temperature over 80°C threshold. Critical temperature high Minor temperature low Major temperature low Temperature over 95°C threshold. Most Shelf Managers shut down the CPM. Temperature under 0°C threshold.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 3 of 14) Number Name 09h SPD DIMM A2 Temp 0Ah SPD DIMM B0 Temp Alarm level Minor temperature high Major temperature high Possible errors or faults Temperature over 72°C threshold. Temperature over 80°C threshold. Critical temperature high Minor temperature low Major temperature low Temperature over 95°C threshold. Most Shelf Managers shut down the CPM. Temperature under 0°C threshold.
B IPMI Commands and Managed Sensors Table 38. Sensor alarms and recommended actions (sheet 4 of 14) Number Name 0Bh SPD DIMM B1 Temp 0Ch 128 SPD DIMM B2 Temp Alarm level Minor temperature high Major temperature high Possible errors or faults Temperature over 72°C threshold. Temperature over 80°C threshold. Critical temperature high Minor temperature low Major temperature low Temperature over 95°C threshold. Most Shelf Managers shut down the CPM. Temperature under 0°C threshold.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 5 of 14) Number Name 0Dh SPD DIMM C0 Temp 0Eh SPD DIMM C1 Temp Alarm level Minor temperature high Major temperature high Possible errors or faults Temperature over 72°C threshold. Temperature over 80°C threshold. Critical temperature high Minor temperature low Major temperature low Temperature over 95°C threshold. Most Shelf Managers shut down the CPM. Temperature under 0°C threshold.
B IPMI Commands and Managed Sensors Table 38.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 7 of 14) Number Name 13h CPU ProcHot Alarm level Minor temperature high Major temperature high Possible errors or faults Temperature over 65°C threshold. Temperature over 72°C threshold. Critical temperature high Temperature over 100°C threshold. Most Shelf Managers shut down the CPM. Temperature under -5°C threshold. Temperature under -10°C threshold.
B IPMI Commands and Managed Sensors Table 38.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 9 of 14) Number Name 1Ch +3.3V IPMI Alarm level Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 1Dh +3.3V Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 1Eh +1.
B IPMI Commands and Managed Sensors Table 38. Sensor alarms and recommended actions (sheet 10 of 14) Number Name 1Fh +1.8V_CPU Alarm level Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 20h +1.8V_BASE Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 21h +1.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 11 of 14) Number Name 22h +1.5V Alarm level Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 23h +1.5V_DDR3 Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 24h +1.
B IPMI Commands and Managed Sensors Table 38. Sensor alarms and recommended actions (sheet 12 of 14) Number Name 25h +1.1V Alarm level Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 26h +1.1V_VTT Minor voltage high Major voltage high Critical voltage high Minor voltage low Major voltage low Critical voltage low 27h +1.
Sensor alarm troubleshooting B Table 38. Sensor alarms and recommended actions (sheet 13 of 14) Number Name 28h +1.0V_FRONT Alarm level Minor voltage high 2Ch BMC Watchdog Event only 2Dh IPMC Watchdog N/A 2Eh ATCA Physical IPMB ATCA Physical IPMB-L NMI N/A Possible errors or faults Voltage over 1.05V threshold; CPM will not go into M4 state.1 Voltage over 1.10V threshold; CPM will not go into M4 state.1 Voltage over 1.15V threshold; CPM will not go into M4 state.1 Voltage under 0.
B IPMI Commands and Managed Sensors Table 38. Sensor alarms and recommended actions (sheet 14 of 14) Number Name 31h +12V RTM PwrFail Alarm level N/A Possible errors or faults Power problem 32h +3.3V RTM Fail N/A Power problem 33h +12V AMC PwrFail N/A Power problem 34h +3.
Temperature sensor locations B Temperature sensor locations As shown in Figure 18, the CPM uses I2C busses 2 and 3 to access internal temperature information for the DIMMs, CPU cores, and the I/O hub. Table 39 provides additional details about the temperature sensors. Figure 18.
B 140 IPMI Commands and Managed Sensors
CONNECTOR PINOUTS AND JUMPER SETTINGS C Front panel interfaces The front USB and Ethernet interfaces are standard and not detailed here. The console serial port pins are described in Table 40 and illustrated in Figure 19. Table 40. RS-232 serial port connector Description RTS DTR TXD GND GND (Cable Detect) RXD DSR CTS RJ-45 Pin 1 2 3 4 5 6 7 8 DB-9 Pin 8 6 2 5 5 3 4 7 Function CTS RTS DSR DTR RX TX ground ground TX RX DTR DSR RTS CTS Figure 19.
C Connector Pinouts and Jumper Settings Backplane interfaces Backplane connectivity summary This section describes the backplane interface connectivity. Table 41.
Zone 1 P10 connector pinout C Zone 1 P10 connector pinout Table 42.
C Connector Pinouts and Jumper Settings Table 42.
Zone 2 J23 connector pinout C Zone 2 J23 connector pinout Table 44.
C Connector Pinouts and Jumper Settings RTM interface pinout Zone 3 J30 connector pinout Table 45. RTM connector J30 signals Row AB 1 +12V_RTM 2 +12V_RTM 3 4 5 6 +12V_RTM +12V_RTM CD +12V_RTM +12V_RTM SERIAL_0_TX SERIAL_0_RX JTAG_TDI SOCA SOCB INT_0 SERIAL_1_TX SERIAL_1_RX +3.
AMC connector pinout C AMC connector pinout Table 47.
C Connector Pinouts and Jumper Settings Table 47.
AMC connector pinout C Table 47.
C Connector Pinouts and Jumper Settings Table 47.
AMC connector pinout C Table 47.
C Connector Pinouts and Jumper Settings Jumper settings Figure 20 shows the physical location of the strapping header, and Table 48 describes the effect of jumpering each pair of pins. Figure 20. Strapping header Table 48. Jumpering pin pairs Pin pair 1 and 2 3 and 4 5 and 6 7 and 8 9 and 10 11 and 12 13 and 14 15 and 16 17 and 18 19 and 20 152 Effect if pins are jumpered Write protects the BIOS boot block. Power down the CPM before removing the jumper.
FRU INFORMATION D FRU information is stored in non‐volatile memory and is used by the IPMC to locate and communicate with the available FRUs. The CPM stores its FRU information in compliance with these specifications: • IPMI Platform Management FRU Information Storage Definition, v1.0, Revision 1.1 • PICMG 3.0 Revision 2.0 AdvancedTCA Base Specification The rsys‐ipmitool utility can retrieve all FRU information, including backplane E‐Keying and on‐board E‐Keying information.
D FRU Information CPM and FRU device IDs The CPM IPMC contains unique identification information. Table 49 and Table 50 describe those identifiers. Table 49. CPM ID information Field Device Name Device ID Firmware Version IPMI Version IPM Support Product ID Manufacturing ID Value ATCA-4500 or ATCA-4550 or ATCA-4555 011h (ATCA CPU module) 1.5 02Dh 03873 4337 Table 50.
LOW-LEVEL HARDWARE MAP E This appendix provides details for the CPM input and output, main memory maps, and SMBus maps. Additional information is provided for the PCI bus device map, including interrupt lines for the PCI device peripherals. This appendix provides crucial information for the developer who needs to know memory locations of the peripheral devices and their interrupt routing. PCI bus device map Table 51 provides device identification for the CPM’s peripheral connections.
E Low-Level Hardware Map Table 51. PCI device map (continued) Peripheral ICH10R I/O Controller Hub SATA VECI LAN USB UHCI #4 USB UHCI #5 USB UHCI #6 USB EHCI #2 Intel High Definition Audio PCI Express Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 PCI Express Port 5 PCI Express Port 6 USB UHCI #1 USB UHCI #2 USB UHCI #3 USB UHCI #6 USB EHCI #1 DMT to PCI Bridge LPC-Corp ENG.
PCI bus device map E Table 51.
E Low-Level Hardware Map Interrupts This section describes I/O controller hub interrupts, APIC interrupt mapping, and PIC interrupt mapping. I/O controller hub interrupts The I/O controller hub (ICH10R) has two built‐in interrupt controllers: the 8259 Programmable Interrupt Controller (PIC) and the Advanced Programmable Interrupt Controller (APIC).
E APIC interrupt mapping APIC interrupt mapping Table 52 lists the APIC interrupt mapping for the CPM. Table 52.
E Low-Level Hardware Map PIC interrupt mapping Table 53 lists the signals connected to the 8259‐compatible programmable interrupt controller. Table 53.
E I/O map I/O map The hub interface cycles that go to target ranges that are marked as “RESERVED” are not decoded by the ICH; they are passed to the PCI. If a PCI master targets one of the fixed I/O target ranges, it is positively decoded by the ICH in Medium speed. Address ranges that are not marked or specified in Table 54 are not decoded by the ICH unless assigned to one of the variables ranges. Table 54.
E Low-Level Hardware Map Table 54.
I2C and SMBus map E I2C and SMBus map Figure 21 illustrates the SMBus connections and addresses, which are listed in Table 55 on page 164. Figure 21.
E Low-Level Hardware Map Table 55.
I2C and SMBus map E Table 55. I2C and SMBus device addresses (continued) Device PCA9555 (AMC PCIe and RTM PCIe0) PCA9555 (RTM PCIe1) a b Master / slave Slave Bus # IOH SMBus Read address 41h Write address 40h Slave IOH SMBus 43h 42h The three geographical pins GA[2:0] are used to assign to IPMB-L address of the AMC. G=Logic Ground, U=Unconnected, P=Pulled up to P3V3 Management Power. The IPMB-L address of the RTM is assigned in the firmware.
E 166 Low-Level Hardware Map
BIOSCLI2 COMMANDS F This appendix describes the command options and usage for the bioscli2 utility. See Command line utility for changing BIOS settings on page 73 for more information about bioscli2. This is the command syntax: bioscli2 [‐] ([]) ([]) ([]) ([‐n]) Commands Typical commands ‐h Display this help menu. bioscli2 ‐h ‐l List all valid online BIOS settings. ‐lp List all valid online BIOS settings in the Option1 page.
F BIOSCLI2 commands Advanced commands ‐ed Export online BIOS settings to a database/ini file. bioscli2 ‐ed biosdb.ini ‐id Import online BIOS settings from a database/ini file. bioscli2 ‐id biosdb.ini ‐ex Export online BIOS settings to an xml file. bioscli2 ‐ex xmlout.xml ‐ix Import online BIOS settings from an xml file. ‐fl List all valid offline BIOS settings. bioscli2 ‐ix xmlout.xml bioscli2 ‐fl bioscli2dump.rom
Troubleshooting F Troubleshooting Table 56 lists bioscli2 error messages, along with a description of the related error condition and the corrective action. Table 56. bioscli2 error messages Error message insmod: can’t read ‘/lib/modules/ xxx/extra/smiflash/ smiflash_mod.ko’ Error condition Corrective action The smiflash driver is not installed 1. Make the smiflash driver that is embedded into the properly. bioscli2 binary (bioscli2 v1.
F 170 BIOSCLI2 commands
CONFIGURE iSCSI BOOT G This appendix describes how to configure an iSCSI boot device. It applies to an ATCA‐4500, ATCA‐4550, or ATCA‐4555 CPM with an iSCSI storage module installed in the same shelf. These procedures were prepared using an Astute Caspian R1100 iSCSI storage module. Depending on the specific iSCSI module, the commands and displayed information may differ from what is presented in these procedures. The operating system to install is Red Hat Enterprise Linux 5.4 64‐bit, or greater.
G Configure iSCSI Boot Configure the Intel iSCSI boot firmware to connect to the iSCSI device 1. When the CPM reboots, press CTRL‐D to enter the Intel Boot Firmware configuration utility. Note: • Connecting using a serial port requires a USB to RS232 connector. • The iSCSI module interface IP addresses can be discovered with the system show interface all command, or through the iSCSI module’s IPMI sensors. 2. In the iSCSI Port Selection screen, select the primary Oplin fabric network adapter.
Install Red Hat Enterprise Linux G Install Red Hat Enterprise Linux 1. After the RHEL DVD boots, enter the following command: linux text console=ttyS0 asknetwork selinux=no 2. 3. 4. 5. 6. 7. 8. Linux boots and Red Hat's pre‐installation utility runs. Select the appropriate language. Select Local CDROM for Installation Method. Select eth4 ‐ Intel Corporation 82598 10Gbe PCI‐Express Ethernet Controller.
G Configure iSCSI Boot Install support packages 1. Extract the contents of the Promentum software installation tarball containing the support packages (RPMs). 2. Send all RPM packages to the CPM by entering the following command: scp /RPMS/* root@10.100.xx.xxx:/~ 3. Use ssh to connect to the CPM7. Install all support packages using the following command for each required RPM: rpm ‐I .rpm 4. Reboot the CPM. Complete the CPM BIOS configuration 1.
