EPC®-3305 Hardware Reference www.radisys.
EPC, iRMX, INtime, Inside Advantage, and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma, and SAIB are trademarks of RadiSys Corporation. † All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners.
Before you begin This guide provides the information you need to install the EPC-3305 and configure its BIOS. It contains detailed hardware reference information for OEMs, system integrators, and others who use the EPC-3305 as a component of their CompactPCI† bus systems. In addition, this manual assumes that you are familiar with PC sytems based on the Intel x86 architecture and have some familiarity with CompactPCI bus architecture.
EPC-3305 Hardware Reference Appendix E Rear Transition module (RTM) F Re-programming the flash chip Description Describes how to install, configure, and use the Rear Transition Module (RTM). Details how to update or recover your system BIOS, Flash Boot Device (FBD), and Boot Block by re-programming all or part of the EPC-3305’s flash chip Notational conventions This manual uses the following conventions: • Screen text and syntax strings appear in this font.
Before you begin • Other: If you purchased your RadiSys product from a third-party vendor, you can contact that vendor for service and support. About related RadiSys products EPC-3306: The EPC-3306 is a high-performance single-slot CompactPCI module that operates as system controller. It incorporates two PMC sites for flexibility using a variety of PMC modules such as SVGA, LAN adapter or WAN adapters. It offers a choice of three memory configurations to address different needs up to 512 MB.
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Contents Chapter 1: Overview. Feature summary .............................................................................................................................. CompactPCI bus............................................................................................................................... Specifications ................................................................................................................................... 2. 3. 4.
EPC-3305 Hardware Reference Flash boot device ................................................................................................................. BIOS ROM and ROM shadowing ....................................................................................... 443BX host bridge ..................................................................................................................... 443BX PCI bus .......................................................................................
Contents Appendix D: Error messages. Boot failures ..................................................................................................................................... 85. Appendix E: Rear Transition module (RTM). Features ............................................................................................................................................ CPU board I/O ..................................................................................................................
EPC-3305 Hardware Reference Figures Figure 1-1. The EPC-3305....................................................................................................................... 1. Figure 2-1. EPC-3305 CPU board: jumper locations ............................................................................... 6. Figure 2-2. Flash header settings ............................................................................................................. 6. Figure 2-3. Replacing the battery ...............
Contents Tables Table 1-1. EPC-3305 environmental specifications.................................................................................. Table 4-1. 443BX unsupported commands.............................................................................................. Table 4-2. PCI device configuration......................................................................................................... Table 4-3. CPLD I/O ports .................................................................
EPC-3305 Hardware Reference Table A-33. Interrupts ............................................................................................................................. Table A-34. ECP registers........................................................................................................................ Table A-35. ISA Plug and Play................................................................................................................. Table A-36.
1 Overview The EPC-3305, a CompactPCI† Peripheral Processor Board, operates in a 6U peripheral slot of a CompactPCI system. The EPC-3305 hardware is compatible with all major PC software environments including Microsoft† Windows† 95, Windows 98, and Windows NT† 4.0. It can also run other PC operating systems, including Linux†, Solaris†, and DOS. The EPC-3305 includes these subsystems: CPU board A single-slot system controller which plugs into a 6U System Slot of a CompactPCI system.
EPC-3305 Hardware Reference Feature summary This section describes CPU board features. For more information about RTM features, see Appendix E, Rear Transition module (RTM). The EPC-3305 CPU board is a Pentium† III-based, PC-compatible, single slot CompactPCI computer designed for use with CompactPCI bus. The EPC-3305 is an EMC2-based design that accepts a Pentium III based EMC2.
Chapter 1: Overview • • • Front Panel Interface • Blue HS LED • RJ45 for COM-1 • RJ45 for Ethernet 1 • Reset Button National Semiconductor 87309 Super I/O • Two RS-232 serial ports • Floppy drive connection • Intel 82C42 compatible keyboard and mouse controller Programmable Watchdog timer with two programmable timeouts: • The first timeout can be set to provide NMI and/or INIT to CPU allowing for a “soft” reset. • The second timeout forces a “hard” reset.
EPC-3305 Hardware Reference Specifications Table 1-1. EPC-3305 environmental specifications Characteristic Temperature Humidity Airflow Vibration Shock EMC ESD susceptibility1 Radiated susceptibility1 1 4 State Operating Value 0°C to 60°C at point of entry of forced air derated 2°C per 1000 ft (300 m) over 6600 ft (2000m) with sufficient airflow to keep within the termperature specification.
2 Configuration and installation This chapter explains how to install the EPC-3305 in a CompactPCI chassis. When reading this file online, you can immediately view information about any installation topic by placing the mouse cursor over a connector name and clicking. For information about... Go to this page... Setting jumpers and headers............................................................................... 6 Inserting the EPC-3305...................................................................
EPC-3305 Hardware Reference Setting jumpers and headers Flash: MFG Figure 2-1. EPC-3305 CPU board: jumper locations Jumper pins are labeled from the point of view of looking at the front of the connector. Flash The CPU board provides a 2x5-pin header (H2) that you use to re-program the Flash chip. For detailed information about re-programming the flash chip, see Appendix F, Re-programming the flash chip.
Chapter 2: Configuration and installation Function Boot Block Enable Pins 4, 5 Description To enable re-programming of the Boot Block, connect pin 5 (BBEN) to pin 4 (VCC). The BBEN pins are separated to prevent accidental connections of these pins (i.e. they cannot be easily jumpered together). The Boot Block is typically NEVER re-programmed, even when the main and parameter blocks are re-programmed. However, the capability to program the Boot Block facilitates quick changes during manufacturing.
EPC-3305 Hardware Reference • BIOS configuration (For information about setting up the BIOS configuration, see Chapter 3, BIOS configuration) • Driver software installation • Application software installation Your system may be preconfigured by your supplier or you may need to perform these tasks yourself. Maintaining and upgrading the EPC-3305 Removing the EPC-3305 To remove the EPC-3305 from the CompactPCI chassis: 1.
Chapter 2: Configuration and installation 5. Press the new battery into place, positive (+) side up. There is danger of explosion if battery is incorrectly replaced. Replace only with same or equivalent type recommended by RadiSys. Dispose of used batteries according to manufacturer’s instructions. 6. Replace the EPC-3305 in the CompactPCI chassis as described in Inserting the EPC-3305. 7. Restore the CMOS settings as described in the CMOS Save and Restore submenu on page 42.
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3 BIOS configuration The EPC-3305 uses the Phoenix NuBIOS to configure and select various system options. This chapter details the various menus and sub-menus used to configure the system. This chapter is written as though you are setting up each field in sequence and for the first time. Your system may be correctly pre-configured and require very little setup. To revert to the original BIOS settings, select Get Default Values from the Exit menu on page 40. This restores the original BIOS settings.
EPC-3305 Hardware Reference Menu map You set up the BIOS by making selections from the menus shown in the next table.
Chapter 3: BIOS configuration Main Setup menu PhoenixBIOS Setup Utility Main Advanced Main Boot Exit System Time: System Date: [16:17:18] [01/01/1997] BIOS Version 01.00.00 Legacy Diskette A: Legacy Diskette B: [1.44/1.
EPC-3305 Hardware Reference Field LegacyDiskette A LegacyDiskette B Description Identifies the type of floppy disk drive installed as the A: or B: drive. Possible settings include: • Disabled (default for the B: drive) • 1.44/1.25MB 31/2" (default for the A: drive) Note: The 1.25MB 31/2" diskette requires a 3-Mode floppy disk drive. • 1.2MB, 5¼" • 2.
Chapter 3: BIOS configuration Primary/Secondary Master/Slave sub-menus There are a total of four IDE adapter sub-menus for the primary and secondary hard disk controllers, each having a master and slave drive menu. Access this screen to: • See or reconfigure the detailed characteristics of the primary hard disk (select the IDE Adapter 0 Master item from the Main BIOS Setup). • Set up new disks and allow the Setup program to determine the proper settings based on information on the disk.
EPC-3305 Hardware Reference Field Type Cylinders Heads Sectors Maximum Capacity 16 Description Identifies the disk type. You can select one of these: Note: You must press + and - to change this field’s values. • Auto (default): Select this option when you want the POST to query the hard disk for its parameters whenever the POST runs.
Chapter 3: BIOS configuration Field Multi-Sector Transfers LBA Mode Control 32-bit I/O Description Allows the System BIOS to read ahead by the specified number of sectors during disk access. This has the effect of reading more data at once to reduce the absolute number of discrete disk reads performed by the operating system, which may increase system performance.
EPC-3305 Hardware Reference Field Transfer Mode Ultra DMA Mode 18 Description Selects the mode that the System BIOS uses to access the hard disk. You can select one of these: • Standard (default) • Fast PIO 1 • Fast PIO 2 • Fast PIO 3 • Fast PIO 4 • FPIO 3 / DMA 1 • FPIO 4 / DMA 2 Older hard disks only support “Standard”. Newer hard disks adhering to “Fast ATA” or “Enhanced IDE” specifications may support the fast programmed I/O or DMA modes.
Chapter 3: BIOS configuration Keyboard Features sub-menu Use this sub-menu to enable or disable various keyboard features. PhoenixBIOS Setup Utility Main Main Keyboard Features NumLock: Key Click: Keyboard auto-repeat rate: Keyboard auto-repeat delay: F1 ESC Help Exit ↑↓ ←→ Item Specific Help [Auto] [Disabled] [30/sec] [1/2 sec] Select Item Select Menu , , or selects field. -/+ Change Values Enter Select Sub-Menu F9 F10 Setup Defaults Save and Exit Figure 3-3.
EPC-3305 Hardware Reference Field Description Keyboard auto-repeat rate Sets the auto-repeat rate when holding a key down on the keyboard. You can select one of these: • 30/seconds (default) • 26.7/seconds • 21.8/seconds • 18.5/second • 13.3/seconds • 10/seconds • 6/seconds • 2/seconds Keyboard auto-repeat Sets the delay between when a key is pressed and when delay the auto-repeat feature begins.
Chapter 3: BIOS configuration UBE Shadow Control sub-menu Use this menu to specify BIOS shadow options. Shadowing refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This allows the CPU to access the BIOS extensions much more quickly and generally increases system performance if many calls to the BIOS extensions are made.
EPC-3305 Hardware Reference Field BIOS Extension Source Offset Shadow Destination Address BIOS Extension Size 22 Description Controls the location of the user BIOS extension to shadow. You can select one of these: • Disabled (default) • E000h • 0000h • 10000h • 2000h • 12000h • 4000h • 14000h • 6000h • 16000h • 8000h • 18000h • A000h • 1A000h • C000h • 1C000h Controls the destination address of the BIOS extension in shadow memory.
Chapter 3: BIOS configuration Advanced menu This menu contains settings for integrated peripherals, memory shadow, cache, and large disk access mode. You access this menu by selecting Advanced from the Main BIOS Setup menu. PhoenixBIOS Setup Utility Main Advanced Main Boot Ethernet 1 Port: BIOS Reboot: Exit [Auto detect] [Warm Start] Console Redirection I/O Device Configuration PCI Configuration Cache Memory Item Specific Help , , or selects field.
EPC-3305 Hardware Reference Field Description I/O Device Configuration Displays a menu that you use to configure peripheral sub-menu devices. For more information, see I/O Device Configuration sub-menu on page 28. PCI Device Configuration Displays a menu that you use to configure PCI devices. sub-menu For more information, see PCI Device Configuration sub-menu on page 30. Cache Memory sub-menu Displays a menu that you use to control the use of the CPU cache.
Chapter 3: BIOS configuration Field Legacy USB Support Description Determines whether the system supports the Legacy Universal Serial Bus (USB). You can select one of these: • Enabled (default): The system supports the Legacy USB. Select this option only if you use a USB keyboard or mouse, and you use it with an OS that does not have USB drivers. This option reduces system performance due to frequent SMI interrupts (see note below). • Disabled: The system does not support the Legacy USB.
EPC-3305 Hardware Reference Console Redirection sub-menu Options in this menu configure console redirection. PhoenixBIOS Setup Utility Main Advanced Main Boot Com Port Address [On-board COM A] Baud Rate Console Type Flow Control Console connection: Continue C.R. after POST: F1 ESC Help Exit ↑↓ ←→ Exit [PC ANSI] [CTS/RTS] [Direct] [Off] Select Item Select Menu Item Specific Help , , or selects field.
Chapter 3: BIOS configuration Field Flow Control Description Specifies flow control. You can select one of these: • CTS/RTS (default) • XON/XOFF • None Console connection Specifies how the console connects to the system. You can select one of these: • Direct (default): Connects the console directly to the system. • Via modem: Connects the console to the system via a modem. Continue C.R. after POST Determines whether console redirection occurs.
EPC-3305 Hardware Reference I/O Device Configuration sub-menu Use the options in this sub-menu to configure the onboard serial and parallel port and disk controllers. PhoenixBIOS Setup Utility Main Advanced I/O Device Configuration Serial port A: Base I/O address: Interrupt: [3F8] [IRQ 4] [Enabled] Serial port B: Base I/O address: Interrupt: [2F8] [IRQ 4] F1 ESC Help Exit ↑↓ ←→ , , or selects field.
Chapter 3: BIOS configuration Field Interrupt Floppy Disk Controller Base I/O Address Description Configures the serial port interrupt. You can select one of these: • IRQ3 (default, Port B) • IRQ4 (default, Port A) Note: This field displays only if the Serial Port field contains a value of [Enabled]. Determines whether the floppy disk controller is available for use. You can select one of these: • Enabled (default): User configuration. • Disabled: No configuration.
EPC-3305 Hardware Reference PCI Device Configuration sub-menu Use the options in this sub-menu to control the exclusion of the UMB region for PCI or ISA and the exclusion of the IRQs for PCI or ISA. PhoenixBIOS Setup Utility Main Advanced PCI Configuration ISA graphics device installed: PCI IRQ line A: PCI IRQ line B: PCI IRQ line C: PCI IRQ line D: Item Specific Help [No] [Auto Select] [Auto Select] [Auto Select] [Auto Select] , , or selects field.
Chapter 3: BIOS configuration Field PCI/PNP ISA IRQ Resource Exclusion sub-menu Description Displays a menu that you use to control the exclusion of PCI and ISA interrupt resources. For more information, see PCI/PNP ISA IRQ Resource Exclusion sub-menu on page 32. PCI/PNP ISA UMB Region Exclusion sub-menu The PCI/PNP ISA UMB Region Exclusion Sub-Menu controls the exclusion of PCI and ISA UMB regions.
EPC-3305 Hardware Reference PCI/PNP ISA IRQ Resource Exclusion sub-menu The PCI/PNP ISA IRQ Resource Exclusion Sub-Menu controls the exclusion of PCI and ISA interrupt regions.
Chapter 3: BIOS configuration Cache Memory sub-menu The options in this sub-menu control the cacheability of certain memory regions and also the settings of the Level 2 (L2) cache.
EPC-3305 Hardware Reference Field Cache Base 0–512k Cache Base 512–640k Cache Extended Memory Area 34 Description Determines how the system caches base memory in the specified area: You can select one of these: • Write Back (default): Writes and reads to and from system memory are cached, then written to system memory when you perform a write-back operation. Select this option to reduce bus traffic by eliminating unnecessary writes to system memory.
Chapter 3: BIOS configuration Field Cache Memory Regions: A000–AFFF B000–BFFF Description Determines how the system deals with specified memory blocks or shadow1 memory. You can select one of these: • Disabled (default): The system does not cache memory. • USWC Caching: System memory locations are not cached (as with uncacheable memory) and coherency is not enforced by the processor’s bus coherency protocol. Speculative reads are allowed.
EPC-3305 Hardware Reference Field Cache Memory Regions: C800–CBFF CC00–CFFF D400–D7FF D800–DBFF DC00–DFFF 36 Description Memory regions. Determines how the system deals with specified memory blocks or shadow1 memory. You can select one of these: • Disabled (default): The system does not cache memory. • Write Back: Writes and reads to and from system memory are cached, then written to system memory when you perform a write-back operation.
Chapter 3: BIOS configuration Field Cache Memory Regions: E000–E3FF E400–E7FF E800–EBFF EC00–EFFF 1 Description Memory used in the E0000h–EFFFFh DRAM region. Determines how the system deals with specified memory blocks or shadow1 memory. You can select one of these: • Disabled (default): The system does not cache memory. • Write Back: Writes and reads to and from system memory are cached, then written to system memory when you perform a write-back operation.
EPC-3305 Hardware Reference Advanced Chipset Control sub-menu Options in this menu control ?. PhoenixBIOS Setup Utility Main Advanced Main ECC Config: Boot Exit [ECC] Item Specific Help , , or selects field. F1 ESC Help Exit ↑↓ ←→ Select Item Select Menu -/+ Change Values Enter Select Sub-Menu F9 F10 Figure 3-12.
Chapter 3: BIOS configuration Boot menu The Boot menu: • Specifies the order in which the system tries to boot from devices attached to the system. • Specifies the boot order of devices in the same class, such as hard drives. Boot order is assigned from top to bottom, with the uppermost enabled boot device in each class being the boot candidate from that device class.
EPC-3305 Hardware Reference Field Boot order Description Determines the boot order of boot devices. This is the default boot order: 1. Hard Drive 2. Removable Devices 3. ATAPI CD-ROM Drive 4. Network Boot 5. MBA UNDI (Bus 0 Slot 2) 6. MBA UNDI (Bus 0 Slot 3) Exit menu Use the options in this menu to save and exit, or abandon your changes and exit to the system.
Chapter 3: BIOS configuration Field Load Setup Values Discard Changes Save Changes Exit & Update BIOS CMOS Save & Restore sub-menu Description Resets the BIOS values to the original, default values set at the factory, before any suppliers or other end users made changes. Loads the system with the values that existed before this editing session started. You do not exit. Saves to CMOS the edits you made during this session but does not exit the Setup program. Updates the BIOS from a floppy disk.
EPC-3305 Hardware Reference CMOS Save and Restore sub-menu Use the options in this menu to save, restore, or erase CMOS settings in the FBD (Flash Boot Device). PhoenixBIOS Setup Utility Main Exit CMOS Save & Restore CMOS Restore Condition: [Never] Item Specific Help , , or selects field.
4 Theory of operation Chapter 4 Overview The EPC-3305 includes these subsystems: • CPU board: A single-slot peripheral CPU which plugs into a 6U peripheral slot of a CompactPCI system. • Rear Transition module (RTM): A rear I/O transition module which plugs into a rear I/O slot of a CompactPCI system. For more information about the RTM, see Appendix E, Rear Transition module (RTM).
EPC-3305 Hardware Reference Organization Block diagram The next figure shows the division and interconnection of EPC-3305 functions. These are described below. Switching regulator Mobile PIII FSB Intel PIII LPM 443BX host bridge Kybd, Mouse FDD HDR HDR AGP PCI Bank 0 Bank 2 Bank 3 Bank 4 128MByte 128MByte 128MByte 128MByte on-board on-board on-board on-board SDRAM SDRAM SDRAM SDRAM batt.
Chapter 4: Theory of operation Memory map The 232 byte physical address space seen by the Intel Pentium III occupies three areas: 1. From 0 to 1 MB is largely defined by the IBM PC/AT architecture. 2. From 1 to 256 MB depends on how much DRAM is installed in the EPC-3305. 3.
EPC-3305 Hardware Reference The Plug-and-Play ESCD is also stored in the Boot-Block FLASH device in the block addressed from FFFFA000h–FFFFBFFFh. This block is always accessible for re-programming. Use extreme caution when re-programming the flash chip. The Boot Block rarely changes and should not require re-programming. For information about re-programming the Flash chip, see Appendix F, Re-programming the flash chip. A “forced recovery” jumper is provided and is connected to the G-PI2O of the PIIX4.
Chapter 4: Theory of operation The BIOS initialization software copies the ROM contents into DRAM (a process called shadowing) at addresses E0000h–FFFFFh. The VGA BIOS is copied into C0000h–C7FFFh of DRAM. After copying into these areas, the BIOS write-protects them. Subsequent writes to these areas complete successfully but do not alter the data in DRAM. There are two parameter blocks, each 8KB in size, used for BIOS code. 443BX host bridge The Intel 443BX is a 492 pin BGA running on 3.
EPC-3305 Hardware Reference The 443BX generates all control signals (such as ~RAS, ~CAS, ~WE, ~CS, and ~DQM) and multiplexed addresses for the SDRAM array. The address and data flow through the 443BX for all SDRAM accesses. PIIX4E PCI-ISA bridge The Intel PIIX4E is a 324 pin BGA that runs on +3.3V with a reference voltage tied to +5V for +5V signal compatibility. It dissipates a maximum of 1 W.
Chapter 4: Theory of operation controller also generates the ISA refresh cycles. The DMA controller supports two separate methods for handling legacy DMA via the PCI bus: • PC/PCI protocol: Allows PCI-based peripherals to initiate DMA cycles by encoding requests and grants via three PC/PCI ~REQ/~GNT pairs. • Distributed DMA: Allows PCI devices to receive reads and writes to 82C37 registers. The DMA controller also provides support for the serial interrupt scheme typically associated with Distributed DMA.
EPC-3305 Hardware Reference • Extended bank: Contains 128 bytes used as general purpose RAM. Time, calendar, and alarm can be represented in either binary or BCD format. The format is determined by bit 2 of Control Register B. The hour is represented in 12- or 24-hour format, and the format is selected by bit 1 of Control Register B. When changing the format, the time registers must be reinitialized to the corresponding data format. The RTC operates on a 32.768 kHz crystal and a separate battery.
Chapter 4: Theory of operation 21554 to hide subsystem resources from the host processor and to resolve any resource conflicts that may exist between the host and local subsystems.
EPC-3305 Hardware Reference Reset Control register Primary byte offset: DB:D8h Secondary byte offset: DB:D8h Bit 0 Name Secondary Reset R/W R/(WP) 1 Chip Reset R/(WP) Description Secondary bus reset. When 0: The 21554 deasserts s_rst_l. This bit must be cleared by a configuration write in the case when it is set by a configuration write. Otherwise, it clears automatically after 100 msec or when p_rst_l deasserts. When 1: The 21554 asserts s_rst_l.
Chapter 4: Theory of operation CompactPCI Hot Swap The CPU Board can interrupt the local processor with IRQ10 on a hot swap switch event. The hot swap switch is indirectly connected to IRQ10. If enabled, this IRQ line will be asserted as long as the ejector handles are open. The local processes may use this interrupt to perform and orderly shut down. For details of software control for the hot swap interrupt, see Special features on page 56.
EPC-3305 Hardware Reference panel. For the Ethernet channel routed to both the front panel and J5 there is an auto detect circuit, which routes the signal to the appropriate RJ45. Once the autodetect circuit has routed the signal, only a loss of link can cause the auto-detect circuit to re-activated. The Ethernet controllers use PCI interrupts and REQ/GNT signals shown in Table 4-2. PCI Device Configuration. The 82559s have a standard PCI 2.
Chapter 4: Theory of operation onboard battery or the +3.3V power supply voltage can supply power and neither power source affects the other. The battery has an expected battery life of 2 years on continuous battery power. In a system that is powered on much of the time and where the ambient power-off temperature is less than 60°C, the battery is estimated to have a life of 10 years.
EPC-3305 Hardware Reference The keyboard interrupt connects to IRQ1. If enabled, the mouse interrupt utilizes IRQ12. The keyboard and mouse connectors are located on the RTM.
Chapter 4: Theory of operation Table 4-4. CPLD indexes for function registers Index value 0x04 R/W R Function Identifies reset source 0x05 R/W 0x06 R/W Unused BIOS control 0x07 0x08 N/A R/W CompactPCI features 0x09 R/ W bit-5 only Unused 0x0A– 0xFE 0xFF — Enables/disables various interrupts from the CPLD Assigns Hard or Soft reset attribute to various reset sources None Selects which BIOS banks are active, enables/diables WP.
EPC-3305 Hardware Reference (POR) value is zero, indication hard reset. A value of one causes that reset source to generate a soft reset sequence. Table 4-5. Reset control register R/W R/W Index Default 0x05 0x00 FP_RST D7 — D6 — D5 — D4 — D3 FP_RST D2 RTM_RST D1 — D0 WD_RST Selects one of these hard or soft reset attributes for the Front Panel reset switch: 0 (zero) Hard reset. 1 Soft reset.
Chapter 4: Theory of operation When exiting a CPU reset condition, the BIOS or application software can check the Reset Event Register to determine the source of the reset. Table 4-7. Watchdog control register R/W R/W Index Default D7 0x01 0x00 WD_EN WD_EN D6 — D5 — D4 — D3 FP D2 SEL2 D1 SEL1 D0 SEL0 Enables watchdog timer. 0 (zero) Disables the watchdog timer. 1 Enables the watchdog timer. SEL0, 1, 2 Selects watchdog timeout value: Timeout 0.
EPC-3305 Hardware Reference next table defines the bit position to control these features. All bits are active high, with the exception of the ENUM bit. Table 4-9. Local interrupt enables R/W R/W Index Default 0x05 0x04 D7 — D6 IRQ7 D5 — D4 IRQ 11 D3 — D2 INIT D1 IRQ 10 D0 NMI IRQ_7 Enables an interrupt on ENUM from the 21554 drawbridge or CompactPCI backplane. If set to one, an interrupt occurs when ENUM asserts. IRQ_11 Enables IRQ 11 when the CPU ejector latch opens.
Chapter 4: Theory of operation Slot of the CompactPCI chassis. RTM_P Indicates that a Rear Transition Module is installed. It is an active low signal. If zero it indicates that the RTM for the CPU is present in the system. INTS_IN Routes CompactPCI interrupts to the processor. If set to one the CPU receives ~INTA , ~INTB, ~INTC, and ~INTD from the CompactPCI backplane. GA4:0 The CompactPCI Geographical Address pins from the CompactPCI backplane.
EPC-3305 Hardware Reference types (hard, Soft, and POR). Figure 4-2 shows the memory overlay at the top of memory space. Boot Block Flash FFFF,FFFF Strata flash PC BIOS 512K User Flash 512K User Flash 512K User Flash 512K User Flash 512K User Flash 512K User Flash 512K User Flash 111 110 101 100 011 010 001 000 FFF8,0000 BC[2:0] Figure 4-2. BIOS paging Each Flash device has its own write protect mechanism.
Chapter 4: Theory of operation voltage range. The global system reset provides a clean system restart whenever the system becomes unstable due to power. A Linear Technology 1643L Hot Swap power controller provides controlled powering up and down of the CPU board. With its internal FETs for ±12V and external FET gate control for 3.3V and 5V, the power controller ramps power up and down for the CPU board upon insertion or extraction.
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A Chipset and I/O map This appendix contains the port I/O addresses for the address-mapped devices in the EPC-3305. As is standard for the ISA bus, the A[15:0] bits are decoded for the 0200h–03FFh range and A[15] and A[9:0] are decoded for addresses above 8000h. Table A-1.
EPC-3305 Hardware Reference Table A-4. Time/counter functions I/O Addr 0040 0041 0042 0043 Functional group Timer/counter R/W R/W R/W R/W W Usage Counter 0 count Counter 1 count Counter 2 count Command mode Table A-5. Keyboard controller I/O Addr 0060 0061 Functional group Keyboard controller NMI status and control 0064 Keyboard controller R/W R/W R R W R W Usage Data I/O register Reset Xbus IRQ12/M and IRQ1 NMI status NMI control Status register Command register Table A-6.
Appendix A: Chipset and I/O map Table A-8.
EPC-3305 Hardware Reference Table A-13.
Appendix A: Chipset and I/O map Table A-17. CPLD I/O Addr 0180– 018F Functional group CPLD R/W R/W Usage See Table 4-3, CPLD I/O ports on page 56. Table A-18. Primary IDE I/O Addr 01F0 01F1 01F2 01F3 01F4 01F5 01F6 01F7 Functional group Primary IDE R/W R/W R/W R/W R/W R/W R/W R/W R/W Usage Data Error/features Sector count Sector number Cylinder Low Cylinder high Drive/head Status/command Table A-19.
EPC-3305 Hardware Reference Table A-22. Serial I/O (COM 2) port I/O Addr x2FC x2FD x2FE Functional group R/W R/W R R/W Usage Modem control register Line status register Modem status register Table A-23. Secondary IDE I/O Addr 0374 0375 0376 Functional group Secondary IDE R/W R/W Usage Reserved Reserved Alt status/device control Table A-24.
Appendix A: Chipset and I/O map Table A-27. EGA controller I/O Addr x3C4 x3C5 x3C6 Functional group R/W R/W R/W R/W R/W R W R/W R/W R R R/W R/W x3C7 x3C8 x3C9 x3CA x3CC x3CE x3CF Usage Sequencer index Sequencer data Video DAC pixel mask Hidden DAC register DAC state Pixel address read mode Pixel mask write mode Pixel data Feature control readback Miscellaneous output readback Graphics controller index Graphics controller data Table A-28.
EPC-3305 Hardware Reference Table A-32. Serial I/O (COM 1) port I/O Addr 3F8 Functional group COM 1 serial port R/W R W R/W R/W R/W R W R/W R/W R R/W 3F9 3FA 3FB 3FC 3FD 3FE Usage Receiver buffer Transmitter buffer Baud rate divisor latch (LSB) Interrupt enable register Baud rate divisor latch (MSB) Interrupt ID register FIFO control register Line control register Modem control register Line status register Modem status register Table A-33.
Appendix A: Chipset and I/O map Table A-38. 443BX configuration data register I/O Addr Functional group R/W Usage R/W Configuration data register 443BX configuration 0CFC– data register1 0CFF (DWORD only) 1 This I/O location is only active when bit 31 of the 443BX configuration address register is 1.
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B Interrupts The following table shows interrupt assignments for the EPC-3305. Table B-1.
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C Connectors This appendix details the connectors on the EPC-3305 CPU board and gives the signal pinout of each connector. For more information about connectors on the RTM, see Appendix E, Rear Transition module (RTM). This product includes the connectors listed in the table below. When reading this file online, you can immediately view information about any connector by placing the mouse cursor over a connector name and clicking. For information about... Go to this page... Connector locations.............
EPC-3305 Hardware Reference Connector locations Figure C-1 shows the locations of the connectors on the EPC-3305’s CPU board. For information about installing peripherals and jumper settings, see Chapter 2, Configuration and installation. Backplane J3 and J5 CompactPCI J1 and J2 Ethernet RS-232 serial port (COM 1) Reset switch Swap-ready LEDs Figure C-1.
Appendix C: Connectors Backplane J3 and J5 The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 row right angle Hard Metric (HM) connector. The signals on this connector are proprietary and include the USB port, COM1 and COM2 ports, and PMC socket B I/O signals. The next table shows this connector’s pinout. Table C-1.
EPC-3305 Hardware Reference Table C-2.
Appendix C: Connectors Table C-3. Compact PCI J1 connector Pin A B C D E 16 ~DEVSEL GND ~STOP ~LOCK 17 18 19 20 3.3V ~SERR 3.3V AD[12] NC GND AD[15] GND V(I/O)(2)(6) NC 3.3V AD[14] F8 GND GND PAR GND AD[11] ~PERR C/~BE[1] AD[13] AD[10] GND GND GND GND 21 3.3V AD[9] M66EN5 C/~BE[0] GND 22 23 24 AD[7] 3.3V AD[1] GND AD[4] 5V AD[6] 5V AD[0] AD[5] AD[2] ~ACK64 GND GND GND 25 5V ~REQ64 3.3V 5V GND V(I/O)(2) AD[8] 3.3V AD[3] V(I/O)2 ~ENUM Table C-4.
EPC-3305 Hardware Reference Notes: 1 This diagram defines the pin assignments from the front of the system chassis. All pins are medium length (level 2) except connector J1 pins C16 and D15, which are long (level 3) and short (level 1), respectively. 2 The V(I/O) signals are either 5V or 3.3V, depending on the system implementation. 3 The following positions in rows 1-3 of connector P2 are implemented on the System Slot board: A1-3, B2, C1-3, and E1-3.
Appendix C: Connectors Ethernet The DTE RJ-45 phone jack provides support for one 10/100BASE-T Ethernet channel. Table C-5. RJ45 phone jack pin-out 1 2 3 4 5 6 7 8 Pin 1 2 3 4 Signal Transmit+ Transmit– Receive+ Center tap transmit Pin 5 6 7 8 Signal Center tap transmit Receive– Center tap receive Center tap receive RS-232 serial port (COM 1) The RS-232 serial port is an RJ-45 phone jack. Table C-6.
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D Error messages Boot failures The System BIOS attempts to display an error message on the VGA and halts when it encounters the following error conditions: 1. Fixed disk error • No drive connected • Configured for 0 cylinders • Controller reset failed • Drive not ready • Track 0 seek timed out • Drive initialization failed • Drive recalibration failed • Last track seek failed 2. Video error • Color/Mono switch not set correctly 3. Timer error • System timer (0) failed 4.
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E Rear Transition module (RTM) This appendix describes the Rear Transition module (RTM), a single slot rear I/O module which connects to the backside of the J3 and J5 connectors, directly behind the CPU board. This appendix includes the topics listed in the table below. When reading this file online, you can immediately view information about any topic by placing the mouse cursor over a connector name and clicking. For information about... Go to this page... Features........................................
EPC-3305 Hardware Reference Installing and configuring the RTM This explains how to install the EPC-3305 in a CompactPCI chassis. For information about... Go to this page... Inserting the RTM............................................................................................. 88 Removing the RTM........................................................................................... 89 Inserting the RTM To insert the EPC-3305 RTM on the PCIbus backplane. 1.
Appendix E: Rear Transition module (RTM) Removing the RTM Occasionally you may need to remove the RTM to perform maintenance tasks such as replacing the battery. To remove the RTM from the CompactPCI chassis: 1. Press the latch part of the extractors inward until the extractor handle swings out and pivots freely. 2. Pull outward on the extractor handles until the RTM disengages from the rear connector. 3. Slide the RTM out of the CompactPCI chassis.
EPC-3305 Hardware Reference Connectors This details the connectors used by the EPC-3305 RTM and gives the signal pinout of each connector. For information about... Go to this page... Connector locations.......................................................................................... 90 Backplane J3.................................................................................................... 91 Backplane J5.......................................................................................
Appendix E: Rear Transition module (RTM) Backplane J3 The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 row right angle Hard Metric (HM) connector. The signals on this connector are proprietary and include the USB port, COM 1 and COM 2 ports, and PMC socket B I/O signals. The next table shows this connector’s pinout. Table E-1.
EPC-3305 Hardware Reference Backplane J5 The back plane connector J5 routes both Ethernet channels, keybard and mouse, secondary EIDE, and PMC socket A I/O signals to the CompactPCI backplane. The next table shows this connector’s pinout. Table E-2.
Appendix E: Rear Transition module (RTM) H1 (COM 1) Table E-4. H1 (COM 2) pin-out 1 2 9 10 Pin 1 3 5 7 9 Signal Carrier detect Receive data Transmit data Data terminal ready Ground Pin 2 4 6 8 10 Signal Data set ready Request to send Clear to send Ring indicator N.C. IDE (secondary) The secondary IDE connector is a male 44-pin right-angle header located on the RTM. The pins and signals are defined as: Table E-5.
EPC-3305 Hardware Reference Keyboard/mouse The keyboard and mouse connector, located on the RTM’s rear panel, is a 6-pin mini-DIN defined as: Table E-6. Keyboard/mouse pin-out 4 6 2 1 3 5 Pin 1 2 3 Signal Keyboard data Mouse data Ground Pin 4 5 6 Signal +5V Keyboard clock Mouse clock The EPC-3305 keyboard and mouse pins are opposite the laptop industry standard. This allows a keyboard to plug in directly without the pigtail.
Appendix E: Rear Transition module (RTM) PIM (PMC I/O Module) The PIM connector, located on the RTM’s rear panel, accepts a PIM that receives rear I/O from PMC site B, connector J24. The pinout has a one-to-one mapping from PMC site J24 to PIM J24. Table E-7. PIM connector pin-out: J20 1 2 63 64 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal N.C. N.C. +5V N.C. N.C. N.C. GND N.C. N.C. N.C. +5V N.C. N.C. N.C. GND N.C. N.C. N.C. +5V N.C. N.C. N.C.
EPC-3305 Hardware Reference Table E-8.
Appendix E: Rear Transition module (RTM) RS-232 (COM 2) The RS-232 serial port is a male DB-9 DTE. The port is mounted on the RTM and is accessible on the rear panel Table E-9.
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F Re-programming the flash chip F This appendix details how to update or recover your system BIOS, Flash Boot Device (FBD), and Boot Block. You accomplish this by re-programming all or part of the EPC-3305’s flash chip. When reading this file online, you can immediately view information about any topic by placing the mouse cursor over a task and clicking. For information about... Go to this page... About the flash chip ......................................................................................
EPC-3305 Hardware Reference About re-programming the flash chip On rare occasions, part or all of the flash chip contents may require replacement. Use extreme caution when re-programming the flash chip. The Boot Block rarely changes and should not require re-programming. Boot block ESCD BIOS: Re-programs only BIOS-related sections of the flash chip. Boot Block (BB): Re-programs only the Boot Block portion of the flash chip.
Appendix F: Re-programming the flash chip When re-programming the flash chip, follow this process. The rest of this chapter includes detailed instructions for each task: Re-programming the flash chip BIOS What part to re-program ? FBD Boot Block Download biosrec.zip Download bbrec.zip Download fbdrec.zip Create a Flash Boot diskette Which re-program method? Run phlash.exe Set BIOS configuration No monitor or keyboard exists, or the BIOS is corrupt.
EPC-3305 Hardware Reference Before you begin • Ensure that you have the following: • Minimum 2 MB of DRAM to run the re-flash program • A 3.5" 1.44 MB floppy diskette drive attached to or installed in the system • A floppy diskette • Access to the RadiSys web site. To access the RadiSys web site, enter this URL in your web browser: http://www.radisys.
Appendix F: Re-programming the flash chip Creating a Flash Boot diskette Re-programming the flash chip requires a Flash Boot diskette that contains both code to perform the task and data to place in the chip. To create the Flash Boot diskette: 1. Locate the appropriate file from the RadiSys web site and download it to your computer: • biosrec.zip: Select this file when you want to re-program only the BIOS-related files. • fbdrec.
EPC-3305 Hardware Reference Now that you have created a Flash Boot diskette, re-flash your system using the directions for the re-flash method you want to use: Method Using phlash.
Appendix F: Re-programming the flash chip Using phlash.exe to re-program the flash chip 1. If you plan to include the Boot Block when re-programming the flash chip, connect the Boot Block Write Enable pins: Do not install this jumper unless a Boot Block update is required. A BIOS boot block rarely changes and seldom, if ever, requires re-programming. A. Turn system power off, then remove the EPC-3305 from the CompactPCI chassis. B.
EPC-3305 Hardware Reference Using BIOS configuration options to re-program the flash chip 1. If you plan to re-program the Boot Block, connect the Boot Block Write Enable pins: Do not install this jumper unless a Boot Block update is required. A BIOS boot block rarely changes and seldom, if ever, requires re-programming. A. Turn system power off, then remove the EPC-3305 from the CompactPCI chassis. B. Connect these pins: 1 9 2 10 Pins 3 and 8 required to re-program the Boot Block C.
Appendix F: Re-programming the flash chip Using jumpers to re-program the flash chip 1. Install the force recovery jumper: A. Turn system power off, then remove the EPC-3305 from the CompactPCI chassis. B. Locate the BIOS configuration jumper block and connect the appropriate pins: i. To re-program the BIOS or the FBD, connect the Force BIOS Recovery pins: 1 9 2 10 Pins 5 and 6 required to re-program the FBD or BIOS ii.
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Glossary Access Time A factor in measurement of a memory storage device’s operating speed. It is the amount of time required to perform a read operation. More specifically, it is the period of time between which the memory receives a read command signal and the time when the requested data becomes available to the system data bus. Address A number that identifies the location of a word in memory. Each word in a memory storage device or system has a unique address.
EPC-3305 Hardware Reference BIOS Update A process whereby an existing, uncorrupted BIOS image in the flash boot device is overwritten with a new image. Also referred to as a flash update. Bit A binary digit. Boot The process of starting a computer and loading the operating system from a powered down state (cold boot) or after a computer reset (warm boot). Before the operating system loads, the computer performs a general hardware initialization and resets internal registers.
Glossary CHS (Cylinders/Heads/Sectors) A specification of disk drive operating parameters consisting of the number of disk cylinders, disk drive read/write heads, and disk sectors. Default The state of all user-changeable hardware and software settings as they are originally configured before any changes are made. DOS (Disk Operating System) One or more programs which allow a computer to use a disk drive as an external storage device.
EPC-3305 Hardware Reference FPGA (Field Programmable Gate Array) A large, general-purpose logic device that is programmed at power-up to perform specific logic functions. FBD (Flash Boot Device) A flash memory device containing the computer’s BIOS. In the NY1210, a 1 MByte Intel 28F800B5 semiconductor flash memory containing the system and video BIOS images, the BIOS initializing code and the recovery code which allows self hosted reflashing.
Glossary microprocessor to jump to a special program called the interrupt service routine. The microprocessor executes this special program, which normally involves servicing the interrupting device. When the interrupt service routine is completed, the microprocessor resumes execution of the program it was working on before the interruption occurred.
EPC-3305 Hardware Reference PLL (Phase-Locked Loop) A semiconductor device which functions as an electronic feedback control system to maintain a closely regulated output frequency from an unregulated input frequency. The typical PLL consists of an internal phase comparator or detector, a low pass filter, and a voltage controlled oscillator which function together to capture and lock onto an input frequency.
Glossary RTC is typically receives power from a small battery to retain the current time of day when the computer is powered down. Reflashing The process of replacing a BIOS image, in binary format, in the flash boot device. Register An area typically inside the microprocessor where data, addresses, instruction codes, and information on the status on various microprocessor operations are stored. Different types of registers store different types of information.
EPC-3305 Hardware Reference SRAM (Static Random Access Memory) A semiconductor RAM device in which the data remains permanently stored as long as power is applied, without the need for periodically rewriting the data into memory. Symmetrically Addressable SIMM A SIMM, the memory content of which is configured as two independent banks.
N A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Index Numerics 32-bit I/O 17. A access time, defined 109. addresses defined 109. logical, defined 113. physical, defined 114. real mode, defined 114. Advanced Chipset Control sub-menu 25. Advanced menu 23. airflow 4. altitude 4. ANSI, defined 109. arbiter, PCI control 65. autotype, defined 109. B bank switching, BIOS 61. battery 54. replacing 8. BIOS bank switching 61. data area, defined 109. defined 109. extension, defined 109.
EPC-3305 Hardware Reference N A B C D E F G H device configuration, I/O 24. DMA controller, I/O Map 65., 68. driver, defined 111. I J K Dynamic Random Access Memory (DRAM), defined 111. L M N O P Q R S T U V W X Y hard disk, transfer mode 18. header, defined 112. help 2. Hot Swap LED 83. humidity 4. E EDO DRAMs, defined 111. EGA 69. EIDE connector, primary 93. electrostatic discharge, avoiding 5. e-mail address, RadiSys 2. ESCD block 24., 46. ESD, avoiding 5. Ethernet connector 83., 92.
Index N A B C D E F G H L Large Disk Access Mode 25. LBA Mode Control 17. LEDs 59., 83. Local interrupt control register 59. logical address, defined 113. LPT1 41. I J K L M N O P Q R Plug-and-Play 46. port A 67. M main menu, BIOS setup 13. makeboot.exe 103. maximum capacity, viewing 16. memory conventional, defined 110. extended, defined 111. random access, defined 114. shadow 21. system, defined 116. Memory Cache sub-menu 14., 24. memory map 45. MFG jumper 7. minidos.sys 103. modem, connecting 88.
EPC-3305 Hardware Reference N A B C D E F G H I J K S second interrupt controller 67. secondar IDE, I/O map 68., 70. serial I/O (COM 2) port I/O map 69. serial I/O (COM 4) port I/O Map 69. serial port 83., 97. shadowing 47. shock 4. SIMMs defined 115. symmetrically addressable, defined 116. Single In-Line Memory Module (SIMM), defined 115. L M N O P Q R S T U V W X Y transfer mode, hard disk 18. troubleshooting 2. type, disk 16. U UBE Shadow Control Sub-Menu 21. UED, term defined 116.
