Specifications

Chapter 4: Theory of operation
53
CompactPCI Hot Swap
The CPU Board can interrupt the local processor with IRQ10 on a hot swap switch
event. The hot swap switch is indirectly connected to IRQ10. If enabled, this IRQ
line will be asserted as long as the ejector handles are open. The local processes may
use this interrupt to perform and orderly shut down. For details of software control
for the hot swap interrupt, see Special features on page 56.
PCI bus implementation and devices
The CPU board implements a +3.3V, 32-bit local PCI bus. The bus runs at 33 MHz
and has the 443BX as the central resource. The local PCI bus has these peripherals
connected to it:
• Host/PCI bus bridge (described in 443BX host bridge on page 47)
• PCI/ISA bridge
• Two Ethernet controllers
• PCI-to-PCI bridge chip
• Two PMC sites
Table 4-2 describes the on-board devices PCI configuration space. The IDSEL pin
on each device connects to the listed PCI address pin. To select the configuration
registers of a given device, a PCI Configuration Space access must be made with the
device’s corresponding IDSEL address bit set.
1
This device is disabled, but consumes a logical device space as indicated.
PCI Ethernet controllers
Two Intel 82559 fast Ethernet controllers incorporate internal MAC and PHY
interfaces, providing support for 10/100BASE-T connections. The two Ethernet
controllers route their RX/TX pairs to CompactPCI Backplane connector J5. One
of the controllers also routes its RX/TX pair to an RJ45 connector on the front
Table 4-2. PCI device configuration
Peripheral IDSEL Device Function I~INTx Arbitration signals REQ/GNT
Intel BX443 North Bridge PCI
Intel BX443 North Bridge
AGP
1
AD11
AD12
0
1
0
0
–
–
–
–
Intel 82559 Ethernet 1 AD13 2 0 C 0
Intel 82559 Ethernet 2 AD14 3 0 D 1
PMC site A A15 4 0 A,B,C,D 3
PMC site B A16 5 0 A,B,C,D 4
Intel 21154 PCI-PCI bridge AD19 8 0 A 2
PCI/ISA bus bridge (PIIX4E)
PCI/ISA bridge
IDE interface
USB (if enabled)
AD19 10
0
1
2
–
–
~PHLD/~PHLDA
directly from the BX443