Specifications

65
A
Chipset and I/O map
This appendix contains the port I/O addresses for the address-mapped devices in the
EPC-3305. As is standard for the ISA bus, the A[15:0] bits are decoded for the
0200h
–03FFh range and A[15] and A[9:0] are decoded for addresses above 8000h.
Table A-1. First (8-bit) DMA controller
I/O Addr Functional group R/W Usage
0000 DMA Controller 1 R/W DMA 1 channel 0 address
0001 R/W DMA 1 channel 0 count
0002 R/W DMA 1 channel 1 address
0003 R/W DMA 1 channel 1 count
0004 R/W DMA 1 channel 2 address
0005 R/W DMA 1 channel 2 count
0006 R/W DMA 1 channel 3 address
0007 R/W DMA 1 channel 3 count
0008 R
W
DMA 1 command
DMA 1 status
0009 W DMA 1 write request
000A W DMA 1 single mask bit
000B W DMA 1 Write mode
000C W DMA 1 clear byte pointer
000D W DMA 1 master clear
000E W DMA 1 clear mask
000F R/W DMA 1 read/write all mask register
bits
Table A-2. First interrupt controller
I/O Addr Functional group R/W Usage
0020 Interrupt Controller 1 R/W INT 1 control
0021 R/W INT 1 mask
Table A-3. PCI arbiter control
I/O Addr Functional group R/W Usage
0022 PCI arbiter control R/W 433BX PCI arbiter control