Specifications

73
Registers
Registers Specific to the EPC-8A
Registers in the I/O space that are specific to the EPC-8A are defined below. Only
registers 8140h–814Fh are “dual-ported” to both the PC and VME bus. The addresses
shown below are used by the PC port. The VME addresses for the registers 8140h–814Fh
are described later.
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O port
Configuration
ARBPRI RELM ARBM GPO VGA VME-E VME-32 8102h
VME A21–16 Address Reg
VMEbus address bits 21–16 res res 8130h
ID Register, lower
111011008140h
ID Register, upper
101111118141h
Device Type Reg, lower
110001008142h
Device Type Reg, upper
0000000S8143h
Status/Control Reg, lower
SRIE 1 SYSC 1 READY PASS NOSF SRST 8144h
Status/Control Reg, upper
0 MODID SYSR R RESDET 1 1 1 8145h
Reserved, lower
111111118146h
Reserved, upper
111111118147h
Protocol Register, lower
111111118148h
Protocol Register, upper
000111118149h
Response Register, lower
R RRIEN 1 SIG MLCK WRCP FSIG LSIG 814Ah
Response Register, upper
0 1 DOR DIR ERR RRDY WRDY 1 814Bh
Reserved, lower
11111111814Ch
Reserved, upper
11111111814Dh
Message Low Reg, lower
RAM 814Eh
Message Low Reg, upper
RAM 814Fh
Message A31–24 Address Reg
VMEbus address bits A31–24 Address register (WA31-24) 8150h
VME Modifier Register
VME WA23–22 BORD IACK AM5 AM4 AM2 AM1 8151h
VME Interrupt State Reg
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8152h
VME Interrupt Enable Reg
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8153h
VME Event State Register
1 1 VMER SIGR WDT ACFA BERR SYSF 8154h
VME Event Enable Register
1 1 VMER SIGR WDT ACFA BERR SYSF 8155h
Interrupt Generator Register
SLOT1*1111INTERRUPT-OUT 8158h
Unique Logical Address Reg
ULA 815Ch
Module Status/Control Reg
DONE
ENSYS0
1 BTOE WDTR FWDT SWDT 1 815Dh
Signal FIFO Register, lower
RAM 815Eh
Signal FIFO Register, upper
RAM 815Fh
Appendix F
F