Specifications

Programming the VMEbus Interface

5-7

VMEbus Address bits 21-16 Res Res

6. Map the address.

7. Write the data

Microsoft C code for Example 2 -

LWORD addr; /* 32-bit A32 address */

BYTE data;

BYTE far * wptr;

outp(0x8102,(inp(0x8102)|2)); /* set VME E-page enable bit */

outp(0x8150,(WORD)(addr >> 24)); /* A31-A24 */

outp(0x8151,2 | (((addr << 8) >> 30) << 6));

/* A23-A22 and address modifier for A32 supervisory data access */

outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A16 */

wptr = (BYTE far *) (0xE0000000L + (addr & 0X0000FFFFL));

*wptr = data; /* Write through window */

The success of the access can be checked either by enabling BERR as an interrupt or

by looking at the BERR bit in the event state register (8154) after each access.

Low-Level Handling of VMEbus Interrupts

The following is a description of how VMEbus interrupts (IRQ1-IRQ7), VXIbus

message interrupts and error interrupts (BERR, ACFAIL, WDTG, etc.) should be

handled on the EPC-8. Note that, in general, the use of EPConnect is highly

recommended for handling interrupts.

• Enable the appropriate registers (VME Interrupt enable (8153) and VME Event

enable (8155) registers) to allow the interrupts you want to respond to.

• Enable IRQ10 on the EPC's equivalent of the 8259 interrupt controller.

• A VXIbus message interrupt is generated when a master (this EPC-8 or another

master) writes to the Message Low register (16-bit) from the VMEbus. A

message interrupt does not occur when the EPC-8 writes to its own message

• Keep in mind that while PC/AT interrupts are edge sensitive, VMEbus interrupts

are level sensitive. As such, you must ensure that

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