EPC - 6A Hardware Reference RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, OR 97124 (503) 615-1100 FAX: (503) 615-1150 www.radisys.
EPC - 6A Hardware Reference EPC, iRMX, INtime, Inside Advantage and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma and SAIB are trademarks of RadiSys Corporation. † All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners. October 1998 Copyright 1998 by RadiSys Corporation All rights reserved.
Contents Chapter 1: Product Description Specifications.................................................................................................................................................... EPC-6A Hardware Features.............................................................................................................................. Differences between the EPC-6 and the EPC-6A.............................................................................................
EPC-6A Hardware Reference Read-Modify-Write Operations................................................................................................................. VMEbus Interrupt Handler ............................................................................................................................... VMEbus Interrupt Response............................................................................................................................. VMEbus Mapped Registers ...............
Contents Response Registers (814Ah and 814Bh) .......................................................................................................... Message High Registers (814Ch and 814Dh)................................................................................................... Message Low Registers 814Eh and 814Fh) ..................................................................................................... VME Modifier Register (8151h) ...............................................
EPC-6A Hardware Reference Figures Figure 2-1. Figure 3-1. Figure 5-1. Figure B-1. Figure B-2. Jumper locations ..................................................................................................................................................... 6 Boot Process. .......................................................................................................................................................... 9 Block Diagram...............................................................
Chapter 1 Product Description 1 This manual contains the information you need to install and use the EPC-6A VMEbus controller. Additional user and programmer manuals discuss the use of software packages available with the EPC-6A. The EPC-6A, a high-speed VMEbus module based on the Intel 80486DX2 processor, is a redesign of the EPC6 VMEbus module which is based on Intel 80386SX processor. You can use the EPC-6A to: • Perform VMEbus master accesses.
EPC-6A Hardware Reference Specifications This table defines the power and environmental specifications of the EPC-6A. Table 1-1. Specifications Characteristic Temperature Humidity Altitude Vibration Shock Current VME VXI Value operating 0 – 60°C ambient storage –40 – 125°C (without battery; 85°C max with battery operating 0 – 90% noncondensing storage 0 – 95% noncondensing operating 0 – 10,000 ft. (3000 m) storage 0 – 50,000 ft. (15,000 m) operating 0.015 inch (0.38 mm) P-P displacement with 2.
Chapter 1: Product Description • A24/A16/D16/D08 VME master/slave support • Slot 1 system controller functions • One EXM expansion slot It should be noted that, due to mechanical limitations, the EPC-6A cannot support EXMs such as EXM-9, EXM-MX, EXM-16, EXM-23, EXM-19, EXM20, EXM-17.
EPC-6A Hardware Reference Additional References PhoenixBIOS† 4.05 Developer’s Reference, Phoenix Technologies, Ltd., 5/22/95 (NOTE: This document cannot be distributed to customers). PhoenixBIOS 4.0 Technical Reference, Phoenix Technologies, Ltd., 3/15/94 (NOTE: This document can be distributed to customers only upon receipt of written permission from Phoenix Technologies, Ltd.). PhoenixBIOS PICO OAK Porting Guide, Phoenix Technologies, Ltd.
Chapter 2 Installation 2 Before installing your EPC-6A, you should unpack and inspect it for shipping damage. Avoid causing ESD damage: • Remove modules from their antistatic bags only in a static-free environment. • Perform the installation process (described later in this chapter) only in a static-free environment. EPC-6A modules, like most other electronic devices, are susceptible to ESD damage.
EPC-6A Hardware Reference Jumpers The jumpers located on the EPC-6A are used for the following functions: Table 2-1. Jumper locations Jumper Function FLASHWE (JP2(1-2)) FBD write-enable Description Install this jumper to enable writes to the FBD. BB_ENB (JP2(3–4)) FBD boot block write enable Install this jumper to enable writes to the boot block of the FBD. POSTLP (JP2(5–6)) Manufacturing loop enable Install this jumper to enter the manufacturing POST loop.
Chapter 2: Installation 1. Make sure the ejector handles are in the normal non-eject position. (Push the top handle down and the bottom handle up so that the handles are not tilted.) 2. Slide the EPC-6A module into the VME chassis, making sure the top and bottom board edges are in the chassis’ card guides. Use thumb pressure on the handles to mate the module firmly with the VME backplane connector. 3.
EPC-6A Hardware Reference Serial Port Cap Your EPC-6A may have been shipped with a plastic cap over the serial port connector. This cap is a conductive cap that shields the exposed pins in the connector from ESD (electrostatic discharge). You should leave it installed when nothing is connected to the serial port. Connecting Peripherals to the EPC-8 Do not: • Plug any cable or connector into the front panel connectors while the system is powered up.
Chapter 3 3 Operation This chapter contains information about user operation and BIOS setup of the EPC-6A. Initialization Sequence The EPC-6A and its BIOS go through these major initialization steps: The seven-segment display shows information about the EPC-6A’s initialization state. Reset 1. Display 2. Run selftests; display number of test 3. Shadow PicoFlash RFA BIOS extension Catastrophic Errors? Yes Display failure number No Config errors? No Yes Log EXM errors to SRAM 4.
EPC-6A Hardware Reference The EPC-6A performs these major initialization steps: 1. Display At power-up, this display reads 8. When the system begins the POST (Power On Self Test), this number changes. 2. Run selftests; display At various times during the POST, a new code displays in the 7-segment display. For detailed information about displayed codes, see the POST code description. To see a list and explanation of these codes, see Chapter 6, Error Messages. 3.
Chapter 3: Operation 4. Attempt to boot from RFA If the BIOS proceeds down the flash memory path, the flash memory is viewed as a bootable disk device and the BIOS starts the bootstrap process by loading the first 512 bytes into memory location 07C0:0000 and passing control to it. The display blanks before the bootstrap process begins. Once the system completes POST, an INT19 is attempted. This attempts to read the boot sector from the disk.
EPC-6A Hardware Reference System Reset The reset switch performs a hardware reset of the EPC-6A and any EXM module, and then invokes the BIOS initialization process discussed in the previous sections. Removing and reapplying power to the EPC-6A also causes a hardware reset. Note that if the dot, or decimal point, in the lower right corner of the 7-segment LED display is illuminated, an EPC-6A program disabled the reset toggle switch.
Chapter 3: Operation Toggle Switch The front-panel toggle switch has these positions: • Inactive (normal position): • Reset: Suspends the EPC-6A; releasing the switch causes a hardware reset. • Abort: Generates the IRQ11 interrupt. The interrupt position has two purposes. An application program can install an IRQ11 interrupt handler and thus define the switch in an application-specific fashion. The second purpose is a special interpretation of the switch during BIOS initialization after a reset.
EPC-6A Hardware Reference Main RSU Screen The next figure shows the layout of the main remote setup screen; the following tables describes menus and their options. +----------------------------------------------------------------------------+ ¦ RadiSys Controller Setup Program, Version 2.01 ¦ ¦ Copyright 1997 by RadiSys Corporation. All rights reserved. ¦ +----------------------------------------------------------------------------¦ ¦ SYS EPC: 6A CPU: 486DX2 Mem: 640K ¦ ¦ Info BIOS: 4.
Chapter 3: Operation Drive Configuration Edit Drive Menu: 1) Floppy A Choice: 2) Floppy B 3) Fixed C 4) Fixed D Table 3-3. Drive Configuration Function Floppy A: Floppy B: Fixed Disk C: Fixed Disk D: Key A B C D Description Configure Floppy Drive A: (sub-menu) Configure Floppy Drive B: (sub-menu) Configure Fixed Disk C: (sub-menu) Configure Fixed Disk D: (sub-menu) Table 3-4. Configure Floppy Drive A and B Function 360K (5.25) 1.2M (5.25) 720K (3.5) 1.44M (3.
EPC-6A Hardware Reference Edit Subtype Menu: 1) Autodetect Choice: 2) Edit Table 3-6. Edit Subtype Function Autodetect Key A Edit E Description Autodetect drive parameters. Selecting this option means the Remote Setup queries the disk drive for its internal parameters on every bootup. Configure Fixed Disk for Flash (sub-menu).
Chapter 3: Operation ULA Menu: 1) F8 (FE00) 5) FC (FF00) Choice: 2) F9 (FE40) 6) FD (FF40) 3) FA (FE80) 7) FE (FF80) 4) FB (FEC0) 8) FF (FFC0) Table 3-8.
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Chapter 4 Programming Interface 4 This chapter describes the EPC-6A as seen by a program. Wherever possible, users should avoid direct use of most of these facilities. Hardware features in common with standard PCs should be accessed by standard BIOS calls. Hardware unique to EPC-6A, such as the VMEbus interface should be accessed through a variety of software packages and drivers available with the EPC-6A.
EPC-6A Hardware Reference Port 0A Functional group 0B 0C 0D 0E 0F 20 21 24 26 40 41 42 43 60 61 64 70 71 80 81 82 83 87 89 18 Interrupt controller 1 83000 Controller Timer Keyboard controller NMI status Keyboard controller Real-time clock BIOS debug port DMA Usage Command register (R) Single-bit DMA request mask(W) Mode Set byte pointer (R) Clear byte pointer (W) Temporary register (R) Master clear (W) Clear mode reg counter (R) Clear all DMA req mask(W) All DMA request mask Port 0 Port 1 Data regi
Chapter 4: Programming Interface Port 8A 8B 8F A0 Port A1 C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 Functional group Interrupt controller 2 Functional group DMA D6 D8 DA DC DE F0 F1 2F8 Coprocessor COM2 serial port 2F9 2FA 2FB 2FC 2FD 2FE 378 379 37A 3F8 3F9 3FA 3FB LPT1 parallel port COM1 serial port Usage Channel 7 page register Channel 5 page register Refresh page register Port 0 Usage Port 1 Channel 4 address Channel 4 count Channel 5 address Channel 5 count Channel 6 address Channel 6 count Channel 7 a
EPC-6A Hardware Reference Port 3FC 3FD 3FE 8104 8130 8132 8134 8136 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 814A 814B 814C 814D 814E 814F 8151 8152 8153 8154 8155 8156 8157 8159 815A 815B 815C 815D 815E 815F 8380 8381 8382 8383 8384 20 Functional group VME and misc control Usage Modem control register Line status register Modem status register Memory control VME A21–16 address alias address of 8130 alias address of 8130 alias address of 8130 ID low ID high Device type low Device type high Sta
Chapter 4: Programming Interface EPC-6A Registers The next table lists registers in the I/O space specific to the EPC-6A. For detailed information about each register, see Appendix C, Registers.
EPC-6A Hardware Reference */ outp(0x8130,(WORD)((addr << 10) >> 24); /* A21–A16 */ wptr = (BYTE far *) (0xE0000000L + (addr & 0X0000FFFFL)); *wptr = data; /* Write through window */ The success of the access can be checked either by enabling BERR as an interrupt or by looking at the BERR bit in the event state register after each access. Since writes are pipelined, software that looks at the BERR bit should first wait until the DONE bit is set.
Chapter 4: Programming Interface Read-Modify-Write Operations VMEbus RMW (read-modify-write) cycles can be performed through use of the 486DX2’s LOCK instruction prefix with certain instructions along with BS16# being asserted. All of these instructions perform a read followed by a write. When such a read occurs that is mapped to the VMEbus, the EPC-6A treats it as the start of a VME RMW cycle. The next VME access from the 486DX2 is treated as the write that terminates the RMW cycle.
EPC-6A Hardware Reference When the 486DX2 performs a locked access (for example, via an instruction using the LOCK instruction prefix) to the local DRAM, VMEbus slave accesses are held up until the last locked access completes. VMEbus Interrupt Handler Although software available for the EPC-6A shields the user from the details of interrupt handling, the following information is provided for the reader who needs further detail.
Chapter 4: Programming Interface Unlike the 12 input conditions, which are level sensitive inputs, the PC architecture defines the PC interrupts, such as IRQ10, as edge sensitive. This requires special attention if you are writing your own interrupt handlers (for example, if you are not using the functions in the Bus Manager software).
EPC-6A Hardware Reference VMEbus Mapped Registers EPC-6A follows the lead of the VXIbus specification in defining a standard set of configuration registers that are mapped into the VMEbus A16 space and thus accessible by other VMEbus modules. These registers are 16-bit registers occupying 64 bytes of A16 space at a base address defined by the EPC-6A’s logical address. The base address is: 1111 111a aa00 0000 where aaa is the value of the ULA field in the response register at I/O port 814A.
Chapter 5 5 Theory of Operation This chapter specifies other information about EPC-6A operation useful to the system designer. The following diagram shows the major elements of the EPC-6A and data paths among them. RadiSys datapath switch gate array 486DX2 8K cache; Integrated FPU DØ ... 31 A2 ... 31 Reset/abort switch R400 RadiSys highly integrated system controller MDØ ... 4 MB DRAM MAØ ...
EPC-6A Hardware Reference also contains Datalight ROM-DOS (version 6.22, revision 2.1) as a 250KB portion of the memory space. The intent of the flash memory is to hold application programs in a standard file-system format, as opposed to being directly user accessible. Software drivers are provided with the EPC-6A for this purpose. Flash Boot Device The 28F004BV-T contains two 8KB parameter blocks. Block 1 is used for System BIOS code storage and is not available for application use.
Chapter 5: Theory of Operation Interrupts The following table shows interrupt assignment. Table 5-1.
EPC-6A Hardware Reference VMEbus Interface The EPC-6A connects to the VMEbus J1 connector. All of the VMEbus signals and voltages on this connector are used except for SERCLK, SERDAT, and +5V STDBY. The EPC-6A, when configured as an A24 slave, responds with BERR if another bus master attempts a D32 access into the EPC-6A’s memory. It also responds with BERR if another master does an access that would map to other than DRAM within the EPC-6A.
Chapter 5: Theory of Operation VMEbus Timing The following table contains some illustrations of the duration of VMEbus operations. The times were measured with the EPC-6A in the ROR bus-release mode. Table 5-2.
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Chapter 6 6 Error Messages This chapter lists error and warning messages, alphabetized by message text. These are messages generated by the BIOS and MS-DOS that may be related to your hardware configuration. CMOS checksum invalid Something in the nonvolatile CMOS RAM is incorrect. Run the BIOS setup program to determine what is wrong, and correct it. If the error occurs repeatedly, the EPC-6A’s battery has failed. This error is available only on a VGA screen.
EPC-6A Hardware Reference Code 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 Description DRAM initialization DRAM 0- and F-page test DRAM byte enable logic test Copy ROM Copy ROM Copy ROM Copy ROM Copy ROM Copy ROM Clear 8042 interface Reset 8042 interface PC hardware initialization Video interface initialization Timer test CMOS shutdown test DMA test DMA test DMA page registers test does not occur Code Description 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C Interrupt controller test
Chapter 6: Error Messages Beep code 1-3-1-3 1-3-4-1 1-3-4-3 1-4-1-1 2-1-2-3 2-2-3-1 Post code 22h 24h 28h 2Ah 2Ch 2Eh 30h 32h 34h 35h 36h 37h 38h 39h 3Ah 3Ch 3Dh 40h 42h 44h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Eh 50h 51h 52h 54h 56h 58h 5Ah 5Ch 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h Checkpoint description Test 8742 Keyboard Controller Set ES segment to register to 4GB Autosize DRAM Clear 512KB base RAM Test 512KB base address lines Test low byte of 512KB base memory Test high byte of 512KB base memory Test
EPC-6A Hardware Reference Beep code 1-2 Post code 74h 76h 7Ah 7Ch 7Eh 80h 82h 84h 85h 86h 88h 8Ah 8Ch 90h 91h 92h 93h 94h 95h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A8h AAh ACh AEh B0h B2h B4h B5h B6h B8h BCh BEh BFh C0h Checkpoint description Test real-time clock Check for keyboard errors Test for key lock on Set up hardware interrupts vectors Test coprocessor if present Disable onboard I/O ports Detect and install external RS232 ports Detect and install external parallel ports Initialize PNP ISA devices Re-i
Chapter 6: Error Messages Beep code Post code D2h D4h D6h D8h DAh DCh Checkpoint description Unknown interrupt error Pending interrupt error Initialize option ROM error Shutdown error Extended Block Move Shutdown 10 error Table 6-4.
EPC-6A Hardware Reference Item FLASH directory Filename README.TXT 6A_V102.ZIP ROMDOS disk EPCONTRL disk 40 ROMDOS Description Text file that describes the RFA image and recovery procedures A factory default zipped (archived) RFA image that you must unzip before use. The readme file explains how to extract this file. Once unzipped, you can upload this file to the RFA via forced recovery. A collection of utilities, drivers, system files, and documentation that make up the ROMDOS operating system.
Chapter 7 Support and Service 7 In North America Technical Support RadiSys maintains a technical support phone line at (503) 615-1100 that is staffed weekdays (except holidays) between 8 AM and 5 PM Pacific time. If you have a problem outside these hours, you can leave a message on voice-mail using the same phone number. You can also request help via electronic mail or by FAX addressed to RadiSys Technical Support. The RadiSys FAX number is (503) 615-1150. The RadiSys E-mail address is support@radisys.
EPC-6A Hardware Reference Quick Exchange services (immediate shipment of a loaner unit while the failed product is being repaired) or other extra-cost services can be arranged, but need to be negotiated in advance to allow RadiSys to pool the correct product configurations. RadiSys does not maintain a general “loaner” pool. Units are available only for customers that have negotiated this service in advance.
Chapter 7: Support and Service and return the product to us, freight prepaid, with the RMA number clearly marked on the exterior of the package. If possible re-use the original shipping containers and packaging. In any case, be sure you follow good ESD-control practices when handling the product, and ensure that anti-static bags and packing materials with adequate padding and shock-absorbing properties are used.
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Appendix A A Connectors This chapter specifies the details of the connectors and headers on the EPC-6A The EXMbus connector is not defined here; its definition is available upon request. Front Panel LEDs The EPC-6A has four discreet LEDs in the front panel’s top left corner. The front panel also contains a seven-segment LED display. For detailed information about the sevensegment LED display, see Front Panel Indicators on page 12. Table A-1.
EPC-6A Hardware Reference Keyboard Connector The standard PS2 keyboard connector, available in the front panel, is a 6-pin mini-DIN connector defined as follows: Table A-3. Keyboard Pin-out Pin 1 2 3 Signal Data Not used Ground Pin 4 5 6 Signal +5V Clock Not used Serial port connectors The next table defines the DB-9 COM1serial port connector. Table A-4.
Appendix B About the Flash Boot Device B This appendix describes how to reflash the Flash Boot Device (FBD) which contains the EPC-6A System BIOS and the picoFlash BIOS extension.
EPC-6A Hardware Reference Main Block #1 and #2 are reserved. The EPC-6A employs Phoenix PicoBIOS version 4.05, implemented as a flash BIOS using the 4 Mb (512 KB) Intel 28F004 SmartVoltage Boot Block. The Flash Boot Device (FBD) contains a 16 KB boot block which holds the BIOS initializing and recovery code Main block #3 contains an 8KB RadiSys manufacturing BIOS and the PicoFlash BIOS extension. The system BIOS code image resides in main block 4. Parameter blocks 1 & 2 contain the System BIOS code.
Appendix B: About the Flash Boot Device • Bootblock • System BIOS and BIOS extensions, Main Blocks 3-4, Parameter block 1 & 2 • FBD, the entire 512K (minus the 16K bootblock) device is reflash, no attempt is made to reprogram the bootblock. • RFA • CMOS Images suitable for update or recovery use absolute binary format (8-bit data, little endian byte ordering).
EPC-6A Hardware Reference • Enable FBD recovery when the system cannot boot to a DOS-compatible operating system. Perform the force update flash recovery process by connecting a null modem serial cable between the EPC-6A’s COM1 port and a source computer on which is installed an SCP that supports the Xmodem protocol. The SCP should also support terminal emulation, as the source computer serves only as a remote console during the flash recovery process.
Appendix B: About the Flash Boot Device you reflashed the FBD boot block. When you power up the system, it boots with the recovered BIOS images. Note that the message: “Image has exceeded target size, Image is being truncated” is normal; this alerts the user that the bootblock was not reflashed.
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Appendix C Registers C Use this table to locate information about EPC-6A registers in the I/O space. Register Page Overview .................................................................................................................................. 54 Memory Control Register (81004h).......................................................................................... 54 VME A21–16 Address Register (8130h)..................................................................................
EPC-6A Hardware Reference Overview Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing to it has no effect. Unless otherwise noted, all registers and bit values are readable and writeable.
Appendix C: Registers CDEN If set, the flash memory is accessible. If clear, writes to the flash data register have no effect and reads from it return an unpredictable value. VME A21–16 Address Register (8130h) VME A21–16 Address Reg VMEbus address bits 21–16 res res When an access is performed by the EPC-6A in its “E page” (address range 0E0000– 0EFFFF), the access is mapped onto the VMEbus.
EPC-6A Hardware Reference ARBPRI Arbitration priority. This defines the level at which theEPC-6A arbitrates for the VMEbus. This value... 11 10 01 00 Means... 3 2 1 0 Like for RELM, altering this field via the VME-mapped location of this register has no effect. RDY This is a RAM bit defined by the VXI specification. In a VXIbus software environment, if RDY=1 and PASS=1, the EPC-6A is ready to accept VXIdefined messages. The VMEbus user needn’t be concerned with this and the next bit.
Appendix C: Registers Protocol Registers (8148h and 8149h) Protocol Register, lower 1 1 1 1 1 1 1 1 Protocol Register, upper 0 1 0 1 1 1 1 1 This read-only register is defined by the VXIbus specification. In VXI systems, it defines the EPC-6A as being a servant and commander, having no signal register, being a bus master, and not providing fast handshake mode.
EPC-6A Hardware Reference Message High Registers (814Ch and 814Dh) Message High Reg, lower Message High Reg, upper This register is an extension of the following register for 32-bit messages. An access to this register clears flag ABMH in the response register.
Appendix C: Registers For compatibility with other EPCs, when writing to this register assign 0 to reserved bit 5 and 1 to reserved bit 3. VME Interrupt State Register (8152h) VME Interrupt State Reg IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR This read-only register defines the state of the VMEbus and message interrupts. IRQx If clear (0), the associated VMEbus interrupt line is asserted. MSGR If clear (0), a message interrupt is being signalled.
EPC-6A Hardware Reference Module Status/Control Register (8156h) Module Status/Control Reg DONE AS DS0 DS1 res res FWDT ENRE This register contains miscellaneous status and control bits. DONE This read-only bit is 0 whenever the EPC-6A has a VMEbus access outstanding. It is used for determining when a pipelined VMEbus write is complete. AS This read-only bit is 1 whenever the VMEbus AS (address strobe) signal is asserted. It may be used for bus monitoring.
Appendix C: Registers Flash Data Register (8383h) Flash Data Register This read/write register is used to access the byte in the flash memory array addressed by the FS address registers. A read returns the value of the addressed byte if bit CDEN in the memory control register is set; otherwise the read returns an unpredictable value. A write to this register writes to the addressed byte if bit CDEN is set and if the flash write-protect jumper is not installed on the board.
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Index A C A16 28 A24 23, 55 ACFAIL 26, 59 Address modifier 23, 25, 58 Address strobe 60 Altitude 1 Arbitration mode 56 Arbitration priority 56 Cache 25 CMOS RAM 10, 30 error 35 COM1 31, 46 COM2 31, 46 Commander 57 Configuration information 10 Configuration registers 28 Coprocessor 29 Current 1 B Backplane jumpers 7 Battery cell type 30 failure 35 header 5 holder 30 life 30 removal 30 replacement 30 BERR 24, 25, 26, 32, 59 Big endian 24 BIOS force update flash recovery process defined 49 initialization 9
EPC-6A Hardware Reference reflashing processes defined 49 reflashing the 47 Flash memory access protection 61 address registers 60 booting from 10 components 30 data register 61 jumper 5 write protection 5 write-protect jumper 61 Front-panel indicators 12 Front-panel switch 12, 13 FS address registers 60 H Hardware reset 12, 61 Humidity 1 Lock 57 LOCK instruction prefix 25, 26 loop. See internal loop.
Index Round-robin arbitration 56 TOD clock 30, 35 Toggle switch 13, 31, 61 S Self accesses 25 Selftest codes displayed 35 failure codes 12 PASS LED 56 Serial port cap 8 ESD shield 8 header 46 terminal 11 Serial port connector 46 Servant 57 Setup program 7, 10, 11, 30 Seven-segment display decimal point 12, 61 failure codes 35 register 61 usage during initialization 9 Seven-segment display purposes 12 Shock 1 Signal register 57 Slave 25, 32 Slave access 45 Slave enable 56 Slave LED 45 Slave offset registe
EPC-6A Hardware Reference use of for self-hosted reflashing 50 66
