Specifications

Chapter 4: Programming Interface
23
Read-Modify-Write Operations
VMEbus RMW (read-modify-write) cycles can be performed through use of the
486DX2’s LOCK instruction prefix with certain instructions along with BS16# being
asserted. All of these instructions perform a read followed by a write. When such a read
occurs that is mapped to the VMEbus, the EPC-6A treats it as the start of a VME RMW
cycle. The next VME access from the 486DX2 is treated as the write that terminates the
RMW cycle. For this reason, RMW accesses that cross a 16-bit boundary will not behave
as expected (because the 486DX2 issues two read accesses).
Slave Accesses from the VMEbus
When SLE in the status/control register is set, the EPC-6A responds to accesses in a 4 MB
range of the A24 space. All types of VME accesses (reads, writes, and read-modify-writes
of all lengths) are supported, except for block transfer cycles and D32 accesses, as a result
of EPC6 compatibility. The address modifier can specify supervisory, nonprivileged,
program, or data.
The 4 MB space occupied by the EPC-6A in the VMEbus A24 space has the same view of
EPC-6A memory as the 486DX2, except that only those accesses that map to EPC-6A
DRAM memory are valid; all others respond with BERR.
Self Accesses Across the VMEbus
Since the EPC-6A’s DRAM can be mapped into the VMEbus A24 address space, the
EPC-6A can access its DRAM in an alternate way—by generating VMEbus accesses to
the appropriate addresses. This can be of use in multiple-processor systems where some of
the EPC-6A’s DRAM is used as shared global memory; it means that the EPC-6A can
access the global memory with the same addresses as used by other processors without
needing to understand that the memory is actually on-board.
This ability is also useful in system checkout (for example, checking operation of the
backplane).
A24 slave accesses result in accesses to the on-board DRAM and never to the cache.
Because the EPC-6A’s cache is a write-through cache, there is never a discrepancy
between data in the cache and the DRAM. When a slave access results in a write
into the DRAM, the EPC-6A automatically purges the cached entry, via cache
invalidation operation.
Read-Modify-Write Operations
The EPC-6A provides synchronization integrity in its local DRAM between accesses from
the 486DX2 into the DRAM and RMW VME accesses from other masters into the DRAM.
When a VMEbus slave read access occurs to the local DRAM, the EPC-6A watches the
VMEbus data and address strobes to determine if the cycle is an RMW cycle. If it is,
accesses by the 486DX2 are held up until the terminating access of the RMW cycle occurs.