EPC -5A Hardware & Software Reference Manual RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, Oregon 97124 Phone: (503) 615-1100 Fax: (503) 615-1150 http://www.radisys.
EPC-5A Hardware & Software Reference Manual EPC, iRMX, INtime, Inside Advantage and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma and SAIB are trademarks of RadiSys Corporation. All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners. October 1998 Copyright 1998 by RadiSys Corporation All rights reserved.
EPC-5A Hardware & Software Reference Manual Hardware Warranty RadiSys Corporation ("RadiSys") warrants the EPC system and component modules to the original purchaser for two years from the product’s shipping date. If an EPC product fails to operate in compliance with its specification during this period, RadiSys will, at its option, repair or replace the product at no charge.
EPC-5A Hardware & Software Reference Manual Table of Contents 1. Product Description ................................................................................................1 Purpose..................................................................................................................1 About this Manual.................................................................................................1 Notational Conventions...................................................................
EPC-5A Hardware & Software Reference Manual Advanced Menu ....................................................................................................37 EXM Menu............................................................................................................39 VME Menu............................................................................................................42 Exit Menu........................................................................................................
EPC-5A Hardware & Software Reference Manual Parallel Port...........................................................................................................88 Keyboard ...............................................................................................................88 Speaker Header .....................................................................................................89 Battery Header ........................................................................................
EPC-5A Hardware & Software Reference Manual List of Illustrations Figure 2-1. Slot-1 Jumper Location ............................................................................... 8 Figure 2-2. Daisy-Chain Signal Concept ....................................................................... 10 Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem ................................ 11 Figure 2-4. VMEbus Backplane Jumper Examples ....................................................... 12 Figure 2-5.
EPC-5A Hardware & Software Reference Manual List of Tables Table 1-1. EPC-5A Environmental and Electrical Specifications.................................. 4 Table 2-1. VME Slots Available.................................................................................... 9 Table 2-2. EPC-5A Jumpers .......................................................................................... 13 Table 5-1. R400EX Features .........................................................................................
1 1. Product Description Purpose This manual was written to provide detailed hardware reference information for OEMs, system integrators, and other engineers using the EPC-5A as a component of their VMEbus systems. The reader should be able to install the EPC-5A and configure the system based on the information in this manual. About this Manual This manual assumes that the reader has good familiarity with PC systems based on the Intel x86 architecture and familiarity with VMEbus architecture.
EPC-5A Hardware & Software Reference Manual 1 1 Chapter 6 Programming the VMEbus Interface. Describes Slot-1 controller functions, slave- and self-accesses, and initializing and programming the VMEbus interface. Chapter 7 Connectors. Describes pinouts for the serial and parallel port connectors, plus the keyboard, speaker, and battery headers. Chapter 8 Upgrades. Lists possible memory upgrades for the EPC-5A. Chapter 9 Troubleshooting and Error Messages.
Chapter 1: Product Description 1 Product Overview The EPC-5A is a PC/AT compatible embedded CPU module containing the following: • 100 MHz Intel486 DX4 processor • RadiSys R400EX chipset • 16 Kbytes of cache and math co-processor on-chip • 4 MB to 256 MB of DRAM memory • Keyboard interface • 2 standard 9-pin DTE serial ports (COM1 & COM2) • 1 standard output-only parallel port (LPT1) • Time-of-day clock with user-replaceable battery • Phoenix 486 BIOS version 4.
EPC-5A Hardware & Software Reference Manual 1 1 Specifications Environmental Temperature Humidity Vibration Shock operating storage operating storage operating storage operating storage 0° to 60° C -40° to 85° C 5 - 95% (non-condensing) 5 - 95% (non-condensing) .015"PP 2.5g (max) 5-2000 Hz .030"PP 5g (max) 5-2000 Hz 30g 11 msec duration 50g 11 msec duration Electrical 100 MHz - DX4 * maximum typical +5V 6.5 A * 5.
Chapter 1: Product Description 6. Support for “User BIOS Extensions” which allows, through BIOS extensions, booting from VME or EXM-2A, etc. Note that EXM-2A’s are supported while the EXM-2 is not. 7. The System BIOS supports disk autotyping and disks larger than 528MB capacity. 8. The Flash File System can be installed as a DOS device driver, therefore flash can be installed as the second drive even when SCSI is the boot device (EXM-16). 9.
EPC-5A Hardware & Software Reference Manual 1 1 NOTES Page 6
2. Before Installation 2 Unpack the EPC-5A and inspect it for shipping damage. ! ▲ CAUTION Do not remove the EPC-5A module from its anti-static bag unless you are in a static-free environment. The EPC-5A, like most electronic devices, is susceptible to electrostatic discharge (ESD) damage. ESD damage is not always immediately obvious. It can cause a partial breakdown in semiconductor devices that might not result in immediate failure.
EPC-5A Hardware & Software Reference Manual Slot-1 Controller Jumper 2 2 P1 Front Panel P2 JP1 Jumpers Figure 2-1. Slot-1 Jumper Location. Additionally, the EPC-5A has another jumper (see Figure 2-1 above) that rarely needs to be changed - the MODID jumper on JP1. The EPC-5A uses pin 30, Row A of the P2 connector for module identification. If the J2 backplane is other than a standard VME or VXI backplane (e.g., a VSB backplane) or Pin 30, Row A is defined for another purpose, remove this jumper.
Chapter 2: Before Installation The EPC-5A plus EXM expansion modules plus any mass storage module can be considered together as a single subsystem. Use the following worksheet to determine the total number of VME expansion interface slots your particular subsystem configuration requires.
EPC-5A Hardware & Software Reference Manual Installing the VMEbus Backplane Jumpers 2 2 The VMEbus specification provides four bus grant signals (BG0 - BG3) and one interrupt acknowledge signal (IACK) via daisy-chain lines. Per the VMEbus specifications, all boards (that plug into the backplane) are required to correctly handle these signals. All slots that do not have a board plugged into the backplane (i.e.
Chapter 2: Before Installation indicates jumper needed 2 Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem. The figure above shows the EPC-5A subsystem. Note that the left-most slot does not require any jumpers. All other slots occupied by the subsystem require all five jumpers be installed.
EPC-5A Hardware & Software Reference Manual BG0 2 2 BG1 BG2 BG3 IACK Single Board Computer that only handles IACK & BG3 "Dumb" Slave Does not handle any of the signals Figure 2-4. VMEbus Backplane Jumper Examples. Once you have determined where the jumpers need to be, you must determine how to jumper your particular backplane.
Chapter 2: Before Installation J1 Connector J1 Connectors BG0 BG1 BG2 BG3 BG0 BG1 BG2 BG3 IACK IACK Figure 2-5. VMEbus Jumpers on Rear Wirewrap Pins. 2 Figure 2-6. VMEbus Jumpers on Front Stake Pins. If the stake pins are on the rear of the backplane, the most common location is in the middle of the J1 connector as shown in Figure 2-5 below. This can be just these pins extended or all pins extended for wirewrapping.
EPC-5A Hardware & Software Reference Manual Jumpers The complete table of EPC-5A jumpers is shown below. Jumpers are shown in Figure 2-1. 2 2 Jumper POST (JP1 [1-2]) FFLASH (JP1[3-4]) BBEN (JP1 [5-6]) FWEN (JP1 [7-8]) Function Manufacturing loop enable Force BIOS recovery MODID (JP1 [9-10]) SPEAKER (H2) SLOT1 (H5) Mod ID routing FBD boot block write enable FBD write enable (except boot block) Speaker Slot 1 Functionality Description Install this jumper to enter the manufacturing POST loop.
3. Installation ! ▲ ▲ CAUTION During all of this installation process, make sure that power to your system is OFF. The EPC-5A is not designed to be inserted or removed while the chassis is powered up. ! ▲ ▲ CAUTION Make sure that the installation process described here is performed in a static-free environment. Do not remove any modules from their anti-static bags unless you are in a static-free environment.
EPC-5A Hardware & Software Reference Manual EXP-BP2 Subplane 3 3 This subplane is used in the smallest configuration, where only the EPC-5A processor module occupies VME slot space. It provides connectivity for two EXM modules within the EPC-5A (e.g., a graphics controller and a network or disk controller). The EXP-BP2 is an L-shaped board with three connectors on each side.
Chapter 3: Installation EXP-BP4 Subplane The EXP-BP4 subplane is used to couple an EPC-5A processor module with an EXP-MX Mass Storage module. The EXP-BP4 is a T-shaped board with four connectors on the front side and three on the rear. 3 After jumpering the backplane, plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the left-most VMEbus slot that the EPC-5A subsystem will occupy.
EPC-5A Hardware & Software Reference Manual EXP-BP3A Subplane The EXP-BP3A subplane is used to add an EXP-MC Module Carrier for the addition of one or two more EXM modules to an EPC-5A processor module. The EXP-BP3A has five connectors on each side. 3 3 After jumpering the backplane, plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the left-most VMEbus slot that the EPC-5A subsystem will occupy.
Chapter 3: Installation EXP-BP5 Subplane The EXP-BP5 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MC Module Carrier and an EXP-MX Mass Storage module. The EXP-BP5 has six connectors on the front side and five on the rear. 3 After jumpering the backplane, plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the left-most VMEbus slot that the EPC-5A subsystem will occupy.
EPC-5A Hardware & Software Reference Manual EXP-BP4A Subplane The EXP-BP4A subplane is used to add either • two EXP-MC Module Carriers or 3 3 • one EXP-AM Adapter Module. The EXP-BP4A has seven connectors on each side. After jumpering the backplane, plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the left-most VMEbus slot that the EPC-5A subsystem will occupy.
Chapter 3: Installation EXP-BP6 Subplane The EXP-BP6 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MX Mass Storage module and either • 3 two EXP-MC Module Carriers or • one EXP-AM Adapter Module. The EXP-BP6 has eight connectors on the front side and seven on the rear.
EPC-5A Hardware & Software Reference Manual EPC-5A Insertion After installing the subplane, the EPC-5A processor module can be inserted into the VMEbus chassis. ! ▲ 3 3 ! ▲ CAUTION Make sure that power to your VME system is off. The EPC-5A module is not designed to be inserted or removed from a live backplane. CAUTION When inserting the EPC-5A module, avoid touching the circuit board and connector pins, and make sure the environment is static-free.
Chapter 3: Installation EXP-MC Module Carrier Insertion If one or more EXP-MC Module Carriers are part of the configuration, they are inserted into the slot(s) immediately to the right of the EPC-5A. The Module Carrier can only be used in a VMEbus slot where the subplane has both EXM connectors. Simply slide the Module Carrier into place and tighten the two top and bottom retaining screws.
EPC-5A Hardware & Software Reference Manual EXP-MX Mass Storage Module Insertion ! ▲ ! ▲ 3 3 CAUTION Handle the mass storage module with care. Avoid sudden drops or jolts. CAUTION When inserting the module, avoid touching the circuit board and connector pins, and make sure the environment is static-free. The EXM-MX Mass Storage module is always inserted as the rightmost module of the EPC-5A subsystem. Insert it so that its rear connector mates with the lower rightmost connector of the subplane.
Chapter 3: Installation Connecting Peripherals to the EPC-5A ! ▲ CAUTION Do not plug in any cable connector into the front panel connectors while the system is powered on. In general, electronic equipment is not designed to withstand potential damage that could arise from fluctuations in power. Never plug in a serial or parallel device, keyboard, transceiver, monitor, or other component while the system is on.
EPC-5A Hardware & Software Reference Manual Serial Ports The front panel contains two DB-9 DTE serial-port connectors. They are standard RS-232 serial communication ports that are 16C450-compatible. Many current PC/AT computers now incorporate 16C550 UARTs. The EPC-5A serial ports may be used for connecting a mouse, modem, serial printer, RS-232 link, etc.
4. BIOS Configuration Introduction The EPC-5A uses the Phoenix NuBIOS to configure and select various system options. This section details the various menus and sub-menus that are used to configure the system. This section is written as though you are setting up each field in sequence and for the first time. Your system may be pre-configured and require very little setup. Some error messages might occur during the execution of the BIOS initialization sequence.
EPC-5A Hardware & Software Reference Manual Main BIOS Setup Menu MAIN 4 IDE Adapter Sub-Menu 4 Memory Shadow Sub-Menu ADVANCED EXM VME EXIT EXM Menu VME Menu Advanced Menu Exit Menu Boot Sequence Sub-Menu Keyboard Features Sub-Menu Figure 4-1. BIOS Setup Menu Map. Use the up and down cursor (arrow) keys to move from field to field. Use the right and left arrows to move between the menus shown in the menu bar at the top of the screen.
Chapter 4: BIOS Configuration Main BIOS Setup Menu The Main BIOS Setup Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
EPC-5A Hardware & Software Reference Manual IDE Adapter 0 Master/Slave: Sub-menus These fields are headings for menus that allow entering complete disk drive information. Once the information is entered for the drive, the entry in the Main Menu shows the drive selected. See IDE Adapter Sub-Menus for more information. Video System 4 4 Use this field to select among the different video options available. Select from EGA/VGA, CGA 80x25, or monochrome. The default is “EGA/VGA”.
Chapter 4: BIOS Configuration IDE Adapter Sub-menus There are a total of two IDE adapter sub-menus for the primary hard disk controller, in a master and slave drive configuration. The EPC-5A hard disk is controlled by the settings for IDE Adapter 0 Master. To see or reconfigure the detailed characteristics of the primary hard disk, select the IDE Adapter 0 Master item from the Main BIOS Setup. The IDE Adapter 0 Master sub-menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
EPC-5A Hardware & Software Reference Manual Type If you are using a pre-configured system, you probably have an IDE hard disk drive. Select “None” if you are not using an IDE hard disk drive. In the case for which you have an IDE disk but cannot employ the “Autotype” feature, then select “User” for the Type and enter the correct drive values for cylinders, heads, sectors/track, and write precompensation from the label attached at the factory.
Chapter 4: BIOS Configuration Memory Shadow Sub-Menu The term “shadowing” refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This allows the CPU to access the BIOS extensions much more quickly and generally increases system performance if many calls to the BIOS extensions are made. The Memory Shadow Sub-menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
EPC-5A Hardware & Software Reference Manual Boot Options Sub-menu Use the Boot Options sub-menu to change the boot sequence options. Select the Boot Options sub-menu by clicking on the Boot Sequence item in the Main BIOS Setup screen. The Boot Options Sub-menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
Chapter 4: BIOS Configuration 2. C: then A: Used to boot from the C: drive, or if none is present, boot from the A: drive. 3. C: only: Used to boot from the C: drive without searching for an A: drive. The default is “A: then C:”. The setting chosen here displays in the Boot Sequence Sub-Menu prompt in the Main BIOS Setup screen. Setup Prompt This option is used to enable or disable the message “Press F2 to enter Setup.
EPC-5A Hardware & Software Reference Manual Keyboard Features Sub-menu The Keyboard Features Sub-menu allows you to enable or disable various keyboard features. To access the keyboard Features menu, select Numlock in the Main BIOS Setup screen. The Keyboard Features Sub-menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
Chapter 4: BIOS Configuration Keyboard auto-repeat delay Use this option to set the delay between when a key is pressed and when the autorepeat feature begins. The options are “1/4 sec”, “1/2 sec”, “3/4 sec”, and “1 sec” . The default delay is “1/4 sec”. When you are finished with this menu, press ESC to exit back to the Main BIOS Setup screen. 4 Advanced Menu This menu controls advanced setup features, such as the 486 internal L1 cache , large disk access modes, and user BIOS extension addresses.
EPC-5A Hardware & Software Reference Manual Large Disk Access Mode If a hard disk larger than 528MB is being used, this selection should be set to “DOS” if running MS-DOS, or set to “Other” if using a different operating system. When set to “DOS”, this selection causes the System BIOS to perform cylinder/head translation if the drive is configured in Setup to have more than 1024 cylinders. The default is “DOS”.
Chapter 4: BIOS Configuration EXM Menu Use the options in this menu to select and configure the available EXM slots. The required configuration information is found in the hardware reference manual shipped with each EXM expansion module. The EXM Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
EPC-5A Hardware & Software Reference Manual Option Byte 1 This option is used to select the first option byte value for the EXM card intended to reside in this slot. Option byte 1 typically defines bit 0 as the card enable bit. Other bits in the option byte are defined by the particular EXM card installed. The proper value of this option for a slot with no EXM card installed is not defined. The value typically used is 00h, the default value.
Chapter 4: BIOS Configuration When using EXMs with configurable interrupts, DMA channels, I/O addresses, and/or memory addresses, avoid conflicts with built-in functions of the EPC-5A. Guidelines are: 1. 2. 3. 4. If an interrupt is needed, use IRQ3, IRQ4, IRQ5, IRQ9, or IRQ15. IRQ7 can be used if the printer port is not being used. IRQ3 should not be used if the COM B port is being used. IRQ4 should not be used if the COM A port is being used. Use DMA channels 1, 3, 6, and 7.
EPC-5A Hardware & Software Reference Manual VME Menu The options in the VME menu are used to configure the EPC-5A’s VME interface. The VME Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
Chapter 4: BIOS Configuration Bus Release This option is used to select the method that the EPC-5A uses to release the VMEbus for other bus masters to use. Selecting “ROR” (Release on Request) allows the EPC-5A to perform better since it releases the VMEbus only if another bus master requests the bus. Selecting “RONR” (Request on No Request – also known as VXI fair-requester mode) causes the EPC-5A to release the VMEbus when its current bus access has completed.
EPC-5A Hardware & Software Reference Manual Exit Menu The options in this menu allow saving settings and exiting, or abandoning changes and exiting to the system, or controlling the backup and restoration of CMOS RAM to the FBD. The Exit Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.
Chapter 4: BIOS Configuration The System BIOS software searches the FBD for the unterminated string “RadiSysCMOS--->” at power-up. This footprint marks the beginning of the CMOS parameter block storage structure. The structure contains a 16-bit CRC of the CMOS RAM data that is calculated at backup time and recalculated at restoration time. If the CRC verification fails, the restoration is skipped. If the System BIOS succeeds in restoring a backup image to CMOS RAM, the system beeps 1 long and 5 short tones.
EPC-5A Hardware & Software Reference Manual Load previous values This option is used to load the system with the previous values before an editing session started. Save Changes 4 4 This option is used to save the edits made during a session. Exit & Update BIOS This option is used to initiate a System BIOS update.
5. Theory of Operation The EPC-5A is a PC/AT compatible processor. Most of the standard functions of the PC architecture is embodied in the RadiSys R400 chip set. In addition, the EPC-5A has two proprietary interfaces: one for the EXM expansion interface and the other for the VMEbus. Processor board The EPC-5A processor board conforms with the VMEbus standard 6U form-factor.
EPC-5A Hardware & Software Reference Manual The core logic system support provided by the R400EX includes the following: RadiSys R400EX PCCompatible Features 5 RadiSys R400EX Core System Support Features 5 Real Time Clock Keyboard/Mouse Controller Cache Shadow PC Speaker/Port B Functionality DRAM Refresh Controller Power Management Support Programmable Chip Select Units (4) IDE Interface Provides Motorola 146818Acompatible real time clock and alarm with 114 bytes of batterybacked CMOS memory.
Chapter 5: Theory of Operation Memory Map The 232 byte physical address space seen by the Intel486 occupies three areas: 1. Addresses between 0 and 1 MB, which are largely defined by the IBM PC/AT architecture. 2. Addresses between 1 MB and 256 MB, which largely depend on how much DRAM is installed in the EPC-5A. 3. Addresses above 256 MB, which provide direct mapping to the VMEbus with a variety of address modifiers and byte orderings.
EPC-5A Hardware & Software Reference Manual For a 32 MB EPC-5A, the extended memory address space is defined as 00100000 01FFFFFF 32764 KB DRAM extended memory For a 64 MB EPC-5A, the extended memory address space is defined as 00100000 20000000 65536 KB DRAM extended memory Note that since the EXM expansion interface has 24 address lines, some of the “uncommitted; mapped to EXM interface” address areas map repeatedly, or wraparound, in the EXM interface's address space.
Chapter 5: Theory of Operation Keyboard Controller The R400EX contains an Intel 8042-compatible keyboard controller. The keyboard controller is addressable at the standard PC-AT architecture I/O addresses of 60h and 64h. Keyboard interrupts are signaled on IRQ1. ROM and ROM Shadowing The EPC-5A contains a 28F004-B*-T Flash Boot Block. The Flash device is mapped into the top of the processor’s 32-bit address space. The Flash device contains the PC BIOS, some peripheral BIOS code, and user extensions.
EPC-5A Hardware & Software Reference Manual If there is more than one BIOS extension, the extension that is located at the highest physical memory location is the first device in the boot chain. Only two drives are visible as BIOS extensions. The following denotes which devices are installed in the system when the devices are enabled. VME Booting: When booting from VME, the second BIOS recognized may be SCSI.
Chapter 5: Theory of Operation Video Controllers The EPC-5A can operate with or without a video controller (such as the EXM-13B or EXM-13A). The BIOS searches for an EXM having an EXM ID in the range E8h-EFh (a range reserved for video controllers). The search is done by EXM slot number, beginning at slot 0. If no EXM video adapter is found, the BIOS looks for a PC add-in card video controller in an EXP-AM Adapter module.
EPC-5A Hardware & Software Reference Manual Resetting the EPC-5A There are a number of ways to reset (reboot) the EPC-5A. 5 5 Power-off, Power-on This causes all boards in the VMEbus to reset. The system runs the poweron self-tests and reboots the operating system. Front-panel Reset button The Reset button causes the EPC-5A to perform a hardware reset. The system runs the power-on self-tests and reboots the operating system. Ctrl+Alt+Del This keyboard sequence is called a “warm boot”.
6. The VMEbus Interface This chapter describes the EPC-5A VMEbus interface as seen by a program. Users should avoid direct use of most of these facilities. Whenever possible, the VMEbus interface should be accessed through the EPConnect software, an easy-to-use, high-level interface that frees you from most machine-dependent considerations. Connectivity The EPC-5A module connects to the VMEbus J1 connector directly and uses all of the defined VMEbus lines except SERCLK, SERDAT, and +5V STDBY.
EPC-5A Hardware & Software Reference Manual When configured as the Slot-1 controller, the EPC-5A detects and terminates data transfer bus timeouts. Once it sees either the DS0 or DS1 lines asserted, a counter is started. If the counter expires before both DS0 and DS1 are deasserted, the EPC-5A asserts the VMEbus BERR signal until both data strobes are deasserted. The duration of the VMEbus timeout counter is 100-120 µsecs.
Chapter 6: The VMEbus Interface It should be noted that the EPC-5A drives all 32 address lines even when performing an A24 or A16 access. Therefore, all the above registers (8150, 8151, 8130) should be set for every access using the VME memory window. Make sure that those registers not directly supplying address lines are set to “FF” values in the appropriate bit positions.
EPC-5A Hardware & Software Reference Manual When accessing the VMEbus in this manner, the source of the VMEbus address lines is defined below. A32 31 3029 0 00 From 486 address bits 29-0 A24 23 0 From 486 address bits 23-0 A16 15 0 From 486 address bits 15-0 Figure 6-2. Source of VMEbus Address Lines (Via Direct Mapping).
Chapter 6: The VMEbus Interface • Big endian, characteristic of Motorola microprocessors and the VMEbus environment in general, where the most-significant data byte (MSB) is stored in the lowest byte address. Address + 3 Address + 2 Address + 1 Address Byte 3 Byte 2 Byte 1 Byte 0 LSB MSB The EPC-5A contains programmable byte-swapping hardware to allow programs to read or write VMEbus memory in either byte order.
EPC-5A Hardware & Software Reference Manual D16 Access D32 Access Addr+1 Addr 32 10 LSB Addr+1 Addr 10 32 486 Address Motorola MSB Address Addr+3 Addr+2 Addr+1 Addr 76 54 32 10 LSB Addr+3 Addr+2 Addr+1 Addr 10 32 54 76 MSB Figure 6-4. Big-Endian Byte-swapping.
Chapter 6: The VMEbus Interface Slave Accesses from the VMEbus When SLE (Slave Enable) in the status/control register (8145h) is set, the EPC-5A’s dual-ported memory will respond to accesses from other VMEbus masters. All types of VME accesses (reads, writes, and read-modify-writes of all lengths) are supported, except for block transfer cycles. The EPC-5A responds to supervisory, non-privileged, program, or data access modes.
EPC-5A Hardware & Software Reference Manual Self Accesses Across the VMEbus Since the EPC-5A’s DRAM can be mapped into the VMEbus A24 or A32 address space, the EPC-5A can access its DRAM in an alternate way - by generating VMEbus accesses to addresses mapped as the EPC-5A’s VME slave memory.
Chapter 6: The VMEbus Interface When a VMEbus slave read access occurs to the local DRAM, the EPC-5A watches the VMEbus data and address strobes to determine if the cycle is an RMW cycle. If it is, accesses by the CPU are held up until the terminating access of the RMW cycle occurs. When the CPU performs a locked access (e.g., via an instruction using the LOCK instruction prefix) to the local DRAM or the cache, VMEbus slave accesses are held up until the last locked access completes.
EPC-5A Hardware & Software Reference Manual Registers Specific to the EPC-5A Registers in the I/O space that are specific to the EPC-5A are defined below.
Chapter 6: The VMEbus Interface Protocol Register, lower 0 1 0 1 1 ABMH 1 1 0 1 1 1 1 8149h Protocol Register, upper LOCK 1 814Ah ULA Response Register, lower 0 0 0 RRDY WRDY 1 814Bh Response Register, upper RAM 814Ch RAM 814Dh RAM 814Eh RAM 814Fh Message High Register, lower Message High Register, upper Message Low Register, lower Message Low Register, upper VMEbus Address bits 31-24 8150h (WA31-24) Message A31-24 Address Register VME WA23-22 BORD IACK AM5 AM4 AM
EPC-5A Hardware & Software Reference Manual VME Event Enable Register DONE AS DS0 DS1 1 1 1 1 (res.) 1 8156h Module Status/Control Register 1 1 1 INTERRUPT-OUT 815Fh Interrupt Generator Register Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing to it has no effect. Unless otherwise noted below, all registers and bit values are readable and writeable.
Chapter 6: The VMEbus Interface VME A21-16 Address Register (8130h) VMEbus Address bits 21-16 Res Res When an access is performed by the EPC-5A in its window (address range 0E0000h0EFFFFh), the access is mapped onto the VMEbus. The least-significant 16 of the VME address bits are provided directly (from the 486), and the remaining 8 (for an A24 access) or 16 (for an A32 access) bits must come from somewhere else. Six of them come from this register.
EPC-5A Hardware & Software Reference Manual A32 If set (1), the EPC-5A’s DRAM is mapped into the VMEbus A32 address space. If clear, the DRAM is mapped into the A24 address space. This readonly bit is influenced by the value stored in the SLAVE-SIZE field of the next register. Device Type Register (8142h & 8143h) 1 0 1 0 Slave Size 0 0 1 0 0 Lower 1 1 1 1 1 Upper This register adheres to the VXIbus specification. Only bit 6 is writeable. Bit 5 is automatically set to match bit 6.
Chapter 6: The VMEbus Interface ARBPRI Arbitration priority. This defines the level at which the EPC-5A arbitrates for the VMEbus. 11 means 3, 10 means 2, 01 means 1, 00 means 0. Like for RELM, altering this field via the VME-mapped location of this register has no effect. READY This is a RAM bit defined by the VXI specification. In a VXIbus software environment, if READY=1 and PASS=1, the EPC-5A is ready to accept VXI-defined messages.
EPC-5A Hardware & Software Reference Manual If A32 and SLE are set, the value in port 8147 defines the base address of the EPC-5A’s memory in the VMEbus A32 address space. This register can hold the values 18 - 1F, which correspond to the base addresses 18000000h - 1F000000h. If A32 is clear and SLE is set, the two low-order bits of SLAVE BASE define the base address of the EPC-5A’s memory in A24 as follows: 00 - 000000h, 01 - 400000h, 10 - 800000h, 11 - C00000h.
Chapter 6: The VMEbus Interface WRDY Write ready. If set, the message registers are armed for an incoming message. When a write occurs into the message-low register, WRDY is cleared and the MSGR interrupt condition is asserted. When the response register is read from the VMEbus, the current value of the register is read, and then LOCK is cleared. The protocol for sending a message to the EPC-5A, if there are multiple potential senders, is the following. The sender first reads the response register.
EPC-5A Hardware & Software Reference Manual VME Modifier Register (8151h) VME WA23-22 BORD IACK AM5 AM4 AM2 AM1 This register is also used when the EPC-5A makes an access through its VME memory window to the VMEbus. Bits 7 and 6 provide VME address bits A23 and A22, respectively. Bits 3-0 define the value placed on the associated VMEbus address-modifier lines.
Chapter 6: The VMEbus Interface VME Interrupt Enable Register (8153h) IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes that the corresponding interrupt is enabled. If any bit in this register is a 1 and the corresponding bit in the interrupt state register is a 0, the EPC-5A IRQ10 interrupt is asserted. Software may then examine the interrupt and event state registers to determine the cause.
EPC-5A Hardware & Software Reference Manual Module Status/Control Register (8156h) DONE AS DS0 DS1 1 1 (res.) 1 This register contains miscellaneous status and control bits. DONE This read-only bit is 0 whenever the EPC-5A has a VMEbus access outstanding. It is used for determining when a pipelined VMEbus write is complete. 6 6 AS This read-only bit is 1 whenever the VMEbus AS (address strobe) signal is asserted. It may be used for bus monitoring.
Chapter 6: The VMEbus Interface VMEbus Mapped Registers The EPC-5A follows the lead of the VXIbus specification in defining a standard set of configuration registers that are mapped into the VMEbus A16 space and thus accessible by other VMEbus modules. These registers are 16-bit registers occupying 64 bytes of A16 space at a base address defined by the EPC-5A’s logical address. The base address is 1111 111a aa00 0000 where aaa is the value of the ULA field in the response register at I/O port 814A.
EPC-5A Hardware & Software Reference Manual 2. A read of the response register from VME clears the LOCK bit (immediately after the current value of the response register is returned). Register State after Reset A hardware reset of the EPC-5A (not a keyboard CTRL+ALT+DEL reset) clears all of the register bits to 0, except for RELM, ARBM, ARBPRI, and the registers at ports 8130h, 8150h, and 8151h, which may be in an undefined state. (All bits, however, are cleared by a power-on reset.
Chapter 6: The VMEbus Interface Low-Level Programming the VMEbus Interface It is recommended that rather than performing accesses in this low-level hardware dependent form, the Bus Manager component of the EPConnect software package be used instead. VMEbus Accesses Two examples are given here including both a verbal description and the Microsoft C source code for performing VMEbus accesses through the memory window. Example #1 performs a 16-bit read from the VMEbus A16 space. 1.
EPC-5A Hardware & Software Reference Manual Bits 3-0 Use the address modifier (in binary form) to determine the appropriate values for these bits. 2Dh = 00101101b Bit 3 Bit 2 Bit 1 Bit 0 (Address Modifier bit 5) (Address Modifier bit 4) (Address Modifier bit 2) (Address Modifier bit 1) = = = = 1 0 1 0 Thus, 8151h should be set to 1100 1010 or CAh. 5. Map the address. Add the A16 address to the memory window address Addr ← E0000000h + A16 address 6. Read the data.
Chapter 6: The VMEbus Interface Example #2 performs a byte (8-bit) write into the VMEbus A32 space. Here the upper 16 bits of the VME address need to be stored in the appropriate registers. 1. Set the VME access bit in register 8104h. 2. Set register 8150h with the value corresponding to the 8 high-order address bits. VMEbus Address bits 31-24 WA31-24 3. Determine the correct address modifier for A32 supervisory access. 4.
EPC-5A Hardware & Software Reference Manual Microsoft C code for Example 2 LWORD addr; /* 32-bit A32 address */ BYTE data; BYTE far * wptr; outp(0x8104,(inp(0x8104)|2)); /* set VME access bit */ outp(0x8150,(WORD)(addr >> 24)); /* A31-A24 */ outp(0x8151,2 | (((addr << 8) >> 30) << 6)); /* A23-A22 and address modifier for A32 supervisory data access */ outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A16 */ wptr = (BYTE far *) (0xE0000000L + (addr & 0X0000FFFFL)); *wptr = data; /* Write through window */ The
Chapter 6: The VMEbus Interface • Keep in mind that while PC/AT interrupts are edge sensitive, VMEbus interrupts are level sensitive. As such, you must ensure that 1) The 8259 interrupt controller is enabled to capture interrupts before a VMEbus interrupt occurs (otherwise VMEbus interrupts will be totally missed) and 2) You must handle all pending VMEbus interrupts before returning from the interrupt handler.
EPC-5A Hardware & Software Reference Manual Start of Loop • Determine the source of the interrupt or event. This can be done by reading the VME Interrupt State register which should be ANDed with the VME Interrupt Enable register. As described above, the VME Event State register and VME Event enable register may also be potential sources for the generation of IRQ10. Keep in mind that all pending interrupts must be handled.
Chapter 6: The VMEbus Interface • Upon returning from the interrupt handling routine, go back to the beginning of the loop until no more interrupts are active. In other words, you must handle all other active interrupts. This includes all other interrupts and errors which come in prior to calling the interrupt handling routine as well as any new interrupts and errors which may occur during this process.
EPC-5A Hardware & Software Reference Manual NOTES 6 6 Page 86
7. Connectors This chapter specifies the details of the connectors on the EPC-5A. Please note, however, that all the connectors adhere to existing standards. The EXM expansion interface connectors are not defined here; their definition is available upon request. Connectors on EXMs and the EXP-MX are described in the separate manuals for those products. All but the battery and speaker headers are on the front panel.
EPC-5A Hardware & Software Reference Manual Parallel Port The DB-25 LPT1 parallel port connector is an Output-Only device defined as: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Signal Strobe DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Acknowledge Busy Paper end Select Pin 14 15 16 17 18 19 20 21 22 23 24 25 Signal Auto line feed Error Initialize printer Select in Signal ground Signal ground Signal ground Signal ground Signal ground Signal ground Signal ground Signal ground Table 7-2. Parallel Port Pinout.
Chapter 7: Connectors Speaker Header The speaker header is located on the EPC-5A circuit board and is defined as: Pin 1 Signal Reference voltage Pin 2 Signal Speaker tone 1 2 Table 7-4. Speaker Header Pinout. Battery Header The battery header is located on the EPC-5A circuit board and is defined as: Pin 1 2 Signal VBATT (key) Pin 3 4 Signal Ground Ground Table 7-5. Battery Header Pinout.
EPC-5A Hardware & Software Reference Manual NOTES 72 72 Page 90
8. Upgrades ! ▲ CAUTION Do not handle the EPC-5A module unless you are in a static-free environment. Memory The EPC-5A can be configured for various memory sizes. The 100 MHz EPC-5A memory configurations use SIMMs with the following specifications: • • • • For 8 MB: For 16 MB: For 32 MB: For 64 MB: 72 pin fast page mode 60 nanosec.
EPC-5A Hardware & Software Reference Manual Figure 8-1. SIMM Memory Location. After upgrading the memory, power up the machine and press F2 to enter the Main BIOS Setup Menu. Verify that the top line of this screen shows the correct amount of memory. Save and reboot. The system reboots and no error messages should be displayed.
9. Troubleshooting & Error Messages Troubleshooting This section deals with problems that you may encounter that do not provide an error message. If an error message is displayed, see the next section of this chapter, Common Error Messages. Always attempt to solve the problem yourself. If you are unable to solve the problem, call RadiSys Technical Support. Make sure you have detailed system configuration available before starting your phone call.
EPC-5A Hardware & Software Reference Manual Symptoms Possible cause(s) Solution System fails at power-up will not run power-on selftest. The system is not getting power. Check the backplane and verify that +5V power is good. Verify that the subplane is fully seated in the VME backplane and the EPC-5A is fully seated in the subplane. Hardware failure. This cannot be diagnosed in the field. Call RadiSys Technical Support. Verify that backplane +12V and -12V are good. Serial port(s) do not work.
Chapter 9: Troubleshooting & Error Messages Common Error Messages This section contains a summary of error and warning messages alphabetized by message text. These are messages generated by the BIOS and MS-DOS that may be related to your hardware configuration. BAD OR MISSING COMMAND INTERPRETER Problem: The DOS operating system cannot find the Command line interpreter. Solution(s): Either COMMAND.
EPC-5A Hardware & Software Reference Manual DISK BOOT FAILURE, INSERT SYSTEM DISK AND PRESS ENTER Problem: No boot disk could be found. Solution(s): This could occur in several different ways. Your hard disk may not have been partitioned into logical drive(s). PCs look for logical drives to boot from. Hard disks are physical drives; partitions are logical drives. Your BIOS setup screen has all disks disabled, or your hard disk is disabled and no floppy diskette is inserted in the A: drive.
Chapter 9: Troubleshooting & Error Messages ERROR INITIALIZING HARD DISK 0 Problem: The IDE disk controller for drive C cannot be initialized. Solution(s): If you are using an EXP-MX mass storage module, ensure that the module is fully seated in the subplane and that the +5V and +12V LEDs indicate that the module has power.
EPC-5A Hardware & Software Reference Manual GENERAL FAILURE READING DRIVE ... Problem: This almost always indicates the presence of an unformatted hard disk partition or diskette. Solution(s): Format the partition or diskette using the utilities supplied by your operating system. INVALID DRIVE SPECIFICATION Problem: You are trying to access a logical drive (e.g., A:, B:, ...) that is not known to the operating system. Solution(s): Select a different logical drive.
Chapter 9: Troubleshooting & Error Messages MEMORY PARITY INTERRUPT AT ... Problem: This could be a software error (reading a nonexistent memory area) or a true hardware failure. Solution(s): Attempt to repeat the error. If the error occurs during the execution of your own proprietary software, verify that the memory location specified in your software is valid.
EPC-5A Hardware & Software Reference Manual NOT READY READING DRIVE ... Problem: This is usually caused by not fully inserting a diskette into the floppy drive. Solution(s): Eject the floppy diskette and reinsert making sure that the diskette seats completely into the floppy drive. PARITY ERROR IN SEGMENT ... Problem: This could be a software error (reading a nonexistent memory area) or a true hardware failure. Solution(s): Attempt to repeat the error.
Chapter 9: Troubleshooting & Error Messages 9 Page 101 9
EPC-5A Hardware & Software Reference Manual Boot Failures The System BIOS attempts to display an error message on the display and halts when it encounters the following error conditions: 1. Fixed disk error Causes : • No drive connected • Configured for 0 cylinders • Controller reset failed • Drive not ready • Track 0 seek timed out • Drive initialization failed • Drive recalibration failed • Last track seek failed 2. Timer error Causes : • System timer (0) failed 3.
Chapter 9: Troubleshooting & Error Messages Phoenix NuBIOS Checkpoints The Phoenix NuBIOS writes a number of checkpoints to I/O port 80h just before they are executed. Note that the execution order of the POST tests generally follows the order listed in the tables below, but not exactly. In addition, some checkpoints are not implemented, but the entire table is presented here for completeness.
EPC-5A Hardware & Software Reference Manual 2-1-2-3 2-2-3-1 9 9 Page 104 38h 39h 3Ah 3Ch 3Dh 40h 42h 44h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Eh 50h 51h 52h 54h 56h 58h 5Ah 5Ch 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 7Ah 7Ch 7Eh 80h Shadow system BIOS ROM Reinitialize the cache Autosize cache Configure advanced system controller registers Load alternate registers with CMOS values Set initial CPU speed Initialize interrupt vectors Initialize BIOS interrupts Check ROM copyright notice Initialize manager
Chapter 9: Troubleshooting & Error Messages 1-2 82h 84h 85h 86h 88h 8Ah 8Ch 90h 91h 92h 93h 94h 95h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A8h AAh ACh AEh B0h B2h B4h B5h B6h B8h BCh BEh BFh C0h Detect and install external RS232 ports Detect and install external parallel ports Initialize PNP ISA devices Re-initialize onboard I/O ports Initialize BIOS Data Area Initialize Extended BIOS Data Area Initialize floppy controller Initialize hard disk controller Initialize localbus hard disk controller Jump to UserPatc
EPC-5A Hardware & Software Reference Manual Beep Code Post Code D0h D2h D4h D6h D8h DAh DCh Checkpoint Description Interrupt handler error Unknown interrupt error Pending interrupt error Initialize option ROM error Shutdown error Extended block move Shutdown 10 error Table 9-2. Phoenix NuBIOS Auxiliary Checkpoint Codes.
10. Support and Service In North America Technical Support RadiSys maintains a technical support phone line at (503) 615-1100 that is staffed weekdays (except holidays) between 8 AM and 5 PM Pacific time. If you have a problem outside these hours, you can leave a message on voice-mail using the same phone number. You can also request help via electronic mail or by FAX addressed to RadiSys Technical Support. The RadiSys FAX number is (503) 615-1150. The RadiSys E-mail address is support@radisys.com.
EPC-5A Hardware & Software Reference Manual Repair Services Factory Repair Service is provided for all RadiSys products. Standard service for all RadiSys products covers factory repair with customers paying shipping to the factory and RadiSys paying for return shipment. Overnight return shipment is available at customer expense. Normal turn-around time for repair and re-certification is five working days.
Chapter 10: Support and Service All non-warranty repairs are subject to service charges. RadiSys has determined that pricing repairs based on time and materials is more cost-effective for the customer than a flat-rate repair charge. When product is received, it will be analyzed and, if appropriate, a cost estimate will be communicated to the customer for authorization. After the customer authorizes the repair and billing arrangements have been made, the product will be repaired and returned to the customer.
EPC-5A Hardware & Software Reference Manual When shipping the product, include the following information: return address, contact names and phone numbers in purchasing and engineering, and a description of the suspected problem. Any ancillary information that might be helpful with the debugging process will be appreciated. Other Countries Contact the sales organization from which you purchased your RadiSys product for service and support.
Appendix A:Chip Set & I/O Map The following defines the I/O addresses decoded by the EPC-5A. It does not define addresses that might be decoded by EXMs and the EXP-MX.
EPC-5A Hardware & Software Reference Manual A A I/O Addr 040 041 042 043 Counter-Timer functions: R400 emulating 8254 of PC/AT Functional group Usage Timer Counter 0 Counter 1 Counter 2 Control (W) I/O Addr 060 Keyboard Port: Intel 8242 emulating 8742 of PC/AT Functional group Usage Keyboard controller Data I/O register 061 NMI status NMI status 064 Keyboard controller Command/status register I/O Addr 070 071 I/O Addr 081 082 083 087 089 08A 08B 08F Time-of-Day Clock: R400 emulating MC6818 of
Appendix A: Chip Set & I/O Map I/O Addr 0A0 0A1 I/O Addr 0C0 0C2 0C4 0C6 0C8 0CA 0CC 0CE 0D0 0D2 0D4 0D6 0D8 0DA 0DC 0DE A Second Interrupt Controller: R400 emulating 8259 of PC/AT Functional group Usage Interrupt controller 2 Port 0 Port 1 Second (16-bit) DMA Controller: R400 emulating 8237 of PC/AT Functional group Usage DMA Channel 4 address Channel 4 count Channel 5 address Channel 5 count Channel 6 address Channel 6 count Channel 7 address Channel 7 count Command/status DMA request Command register
EPC-5A Hardware & Software Reference Manual A A Coprocessor Interface: On the EPC-5A, 486’s built-in coprocessor replaces the 80287 of PC/AT I/O Addr Functional group Usage 0F0 Coprocessor Clear coprocessor busy 0F1 Reset coprocessor I/O Addr 2F8 2F9 2FA 2FB 2FC 2FD 2FE I/O Addr 378 379 37A I/O Addr 3F8 3F9 3FA 3FB 3FC 3FD 3FE Serial I/O (ComB) Port: TI 16C452 emulates PC/AT chipset Functional group Usage COM2 serial port Receiver/transmitter buffer Baud rate divisor latch (LSB) Interrupt enable regi
Appendix A: Chip Set & I/O Map I/O Addr 8130 8132 8134 8136 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 814A 814B 814C 814D 814E 814F 8150 8151 8152 8153 8154 8155 8156 815F A EPC-5A Memory Mapping Registers: No PC/AT equivalent Functional group Usage VME and misc control VME map WA21-16 Alias of 8130 Alias of 8130 Alias of 8130 ID low ID high Device type low Device type high Status/control low Status/control high Slave offset low Slave offset high Protocol low Protocol high Response low Response h
EPC-5A Hardware & Software Reference Manual A A NOTES Page A-6
Appendix B:Interrupts and DMA Channels Interrupts The assignment of interrupts for the EPC-5A is shown in the following table: NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 DRAM parity error, EXM expansion interface I/O channel check timer keyboard IRQ8 - IRQ15 cascade through IRQ2 COM B serial port COM A serial port unassigned usually needed for floppy disk controller LPT1 parallel port clock unassigned VME interrupt/event unassigned unassigned coprocessor used
EPC-5A Hardware & Software Reference Manual DMA Channels The assignment of DMA channels for the EPC-5A is shown in the following table. B B 0 1 2 3 4 5 6 7 unassigned (8-bit) unassigned (8-bit) usually needed for floppy disk (8-bit) usually needed for SCSI disk (8-bit) (Channel 0 - Channel 3 cascade through Channel 4) unassigned (16-bit) unassigned (16-bit) unassigned - not connected to EXM expansion interface (16-bit) Table B-2. EPC-5A DMA Channels.
Appendix C: Flash Boot Device The system BIOS is based on the Phoenix NuBIOS version 4.05 implemented as a Flash BIOS using the Intel 28F004BV-T SmartVoltage Boot Block Flash Device (hereafter referred to as the Flash Boot Device or FBD). System BIOS code and data reside in the 16KB boot block, parameter block #1, parameter block #2 (CMOS data), and the 96KB main block (#4). Additional BIOS extensions are stored in the uppermost 128KB main block (#3).
EPC-5A Hardware & Software Reference Manual The Flash Boot Device is organized according to the following diagram: Physical Address (Real Mode Address) 28F004BV-T Device Offset FFFFFFFFh (FFFFFh) FFFFC000h (FC000h) 16KB Boot Block BIOS Recovery code FFFFBFFFh (FBFFFh) C C 8KB Parameter Block 2 7FFFFh 7C000h 7BFFFh FFFF9FFFh (F9FFFh) FFFFA000h (FA000h) FFFF8000h 8KB Parameter Block 1 (System BIOS) (F8000h) FFFF7FFFh (F7FFFh) 96KB Main Block 4 (System BIOS) 7A000h 79FFFh 78000h 77FFFh FFFE0
Appendix C: Flash Boot Device The following table describes the exact sizes and placement of the various code and data objects present in the FBD: Object Name Boot and Recovery Code CMOS data System BIOS PicoFlash BIOS Extension vROM BIOS Extension Mfg.
EPC-5A Hardware & Software Reference Manual The update process occurs as a self-hosted FBD update when the system can boot to MS-DOS. The Phoenix update program, PHLASH.EXE, may be executed on the EPC-5A after it has booted to MS-DOS. The user may initiate the update by changing to the drive containing the PHLASH.EXE and executing it on the EPC-5A. Note that the PHLASH.
Appendix C: Flash Boot Device The update process is outlined in the following flow chart: start C no CMOS Reflash byte on? no Force jumper installed? yes yes Turn off CMOS Reflash b t Checksum OK? no Do floppy recovery yes Load Reboot Figure C-2. Flash Boot Device Recovery Mechanism.
EPC-5A Hardware & Software Reference Manual System BIOS recovery operates in detail as follows: C C 1. The boot block prepares the system hardware (DMA and interrupt controllers, DRAM, etc.) to boot the recovery floppy. 2. The boot block loads the special boot sector on the recovery diskette (written to the diskette by MAKEBOOT.EXE - a special Phoenix-supplied MS-DOS tool) and jumps into it. 3. The boot sector loads MINIDOS.SYS from the floppy and jumps into it.
Appendix C: Flash Boot Device The Reflash Flash update program requires the /F and /O command line arguments; the /P is optional. This information may be displayed by typing Reflash with no parameters: /F= /O File to be flashed; multiple file names may be specified. Offset to begin flashing; offsets are relative to the lowest address of the flash device; these are not PC addresses. For example, an offset of zero specifies that flashing is to begin at the very first byte of the flash device.
EPC-5A Hardware & Software Reference Manual User BIOS Extensions C C The EPC-5A supports several different boot methods and OSes. In order to boot from VME or flash, it is necessary to first load and execute a BIOS extension. The FBD has an unused 96KB region in main block #3 that lies between the end of the PicoFlash extension and start of the System BIOS that can be used for BIOS extension storage.
Appendix C: Flash Boot Device PicoCard Flash File System The EPC-5A contains a BIOS used to access the Flash as a read/write disk. If the user selects shadowing of the PicoCard memory region, the extension is loaded to initialize the disk. FBD The Setup field named “BIOS Extension Size” in the Advanced menu selects the ending address when added to the “BIOS Extension. Offset in FBD”.
EPC-5A Hardware & Software Reference Manual NOTES C C Page C-10
Appendix D PFormat The EPC-5A supports use of EXM-2A flash cards as Chapter 2 discusses. The supported configurations require the use of appropriate software to provide drivers and a suitable format. This appendix briefly describes the software from RadiSys. The following is a description of how to bring the RFA up using the PICOFA driver. Contents of the distribution diskette: CONFIG.SYS PFA2.SYS PFORMAT.EXE PFA2.BIN REFLASH.EXE - A sample configuration. The device driver. The format utility.
EPC-5A Hardware & Software Reference Manual Step 1B (Load as BIOS extension) Note that if the driver is loaded as a BIOS extension, the system will attempt to boot from the device. This means that the RFA must be formatted and loaded with system files before the driver can be successfully loaded as a BIOS extension. Flash the device driver into the BIOS: Using the REFLASH.EXE (version 2.0+) utility provided on the diskette, issue the following command: REFLASH /F=PFA2.
PFormat Step 2: Format the drive Assuming that the driver loaded successfully (either as a device driver or as a BIOS extension), run the PFORMAT.EXE utility as follows: PFORMAT D: /C /V The /C confirms the format, and the /V switch says to put a volume label on the drive. When the format completes, give the drive a volume label. This should complete the process of making the RFA into a Flash File System. If you are going to use the RFA as a bootable device, the system must be transferred to the RFA device.
EPC-5A Hardware & Software Reference Manual NOTES D D Page D-4
Appendix G: Glossary A Access Time: A factor in measurement of a memory storage device’s operating speed. It is the amount of time required to perform a read operation. More specifically, it is the period of time between which the memory receives a read command signal and the time when the requested data becomes available to the system data bus. Address: A number that identifies the location of a word in memory. Each word in a memory storage device or system has a unique address.
EPC-5A Hardware Reference B Basic Input/Output System (BIOS): Firmware in a PC-compatible computer that runs when the computer is powered up. The BIOS initializes the computer hardware, allows the user to configure the hardware, boots the operating system, and provides standard mechanisms that the operating system can use to access the PC’s peripheral devices. BIOS Data Area (BDA): BIOS Data Area.
Glossary Boot Sequence: The order in which a computer searches external storage devices for an operating system to boot. The boot device must be the first in the boot sequence. Byte: A group of 8 bits. C Central Processing Unit (CPU): A semiconductor device which performs the processing of data in a computer.
EPC-5A Hardware Reference CMOS Save and Restore (CSR): A System BIOS feature that allows the user to backup the contents of CMOS RAM (contained within the real time clock) to the BIOS Flash device to be restored later if necessary (such as when the real time clock battery dies). Cylinders/Heads/Sectors (CHS): A specification of disk drive operating parameters consisting of the number of disk cylinders, disk drive read/write heads, and disk sectors.
Glossary Extended Data Out (EDO): A type of DRAM that allows higher memory system performance since the data pins are still driven when CAS# is de-asserted. This allows the next DRAM address to be presented to the device sooner than with Fast Page Mode DRAM. Extended Memory: The RAM address space, in a computer so equipped, above the 1 MB level. Extended System Configuration Data (ESCD): A block of nonvolatile memory that stores information on the devices found and configured by the Plug and Play BIOS.
EPC-5A Hardware Reference G Gigabyte (GB or GByte): Approximately one billion (US) or one thousand million (Great Britain) bytes. 230 = 1,073,741,824 bytes exactly. H Hang: A condition where the system microprocessor suspends processing operations due to an anomaly in the data or an illegal instruction. Header: A mechanical pin and sleeve style connector on a circuit board. The header may exist in either a male or female configuration.
Glossary Interrupt Request (IRQ): In ISAbus systems, a microprocessor input from the control bus used by I/O devices to interrupt execution of the current program and cause the microprocessor to jump to a special program called the interrupt service routine. The microprocessor executes this special program, which normally involves servicing the interrupting device.
EPC-5A Hardware Reference Memory: A designated system area to which data can be stored and from which data can be retrieved. A typical computer system has more than one memory area. See Conventional Memory and Extended Memory. O Offset: The difference in location of memory-mapped data between the physical address and the logical address. Operating System: See Disk Operating System. P-Q PCI Mezzanine Card (PMC): A new standard form factor for PCI add-in modules.
Glossary Pinout: A diagram or table describing the location and function of pins on an electrical connector. Plastic Quad Flat Pack (PQFP): A popular package design for integrated circuits of high complexity. Power On Self Test (POST): A diagnostic routine which a computer runs at power up. Along with other testing functions, this comprehensive test initializes the system chipset and hardware, resets registers and flags, performs ROM checksums, and checks disk drive devices and the keyboard interface.
EPC-5A Hardware Reference Real Time Clock (RTC): Peripheral circuitry on a computer motherboard which provides a nonvolatile time-of-day clock, an alarm, calendar, programmable interrupt, square wave generator, and a small amount of SRAM. In the EPC30, the RTC operates independently of the system PLL which generates the internal system clocks. The RTC typically receives power from a small battery to retain the current time of day when the computer is powered down.
Glossary Serial Port: A physical connection with a computer for the purpose of serial data exchange with a peripheral device. The port requires an I/O address, a dedicated IRQ line, and a name to identify the physical connection and establish serial communication between the computer and a connected hardware device. A serial port is often referred to as a COM port. Shadow Memory: RAM in the address range 0xC000h through 0xFFFFFh used for shadowing.
EPC-5A Hardware Reference U Universal Serial Bus (USB): A new serial data bus that is intended to eliminate the need for separate serial, parallel, mouse, keyboard, joystick, etc. ports on a PC-compatible. These ports can be conceivably replaced by a few, daisychained USB ports, all with identical connectors but capable of much higher throughput, upwards of 12Mbs. User Editable Drive (UED): A feature of the EPC-5A’s Phoenix NuBIOS.
Index A A16, 3, 58, 59, 60, 72, 77, 78, 79 A24, 3, 58, 59, 60, 63, 69, 70, 72, 78 A32, 3, 58, 59, 60, 63, 69, 70, 72, 78, 81 access time, G-1 ACFAIL, 75, 82 adapter cable, 25 adapter module, 3, 20, 21, 53 address, G-1 address lines, 59 address modifier, 59, 60, 63, 74, 79 address modifiers, 78 address space, 3 address strobe, 76 ANSI, G-1 arbitration mode, 71 arbitration priority, 71 Autotype term defined, G-1 B backplane, 12 backplane jumpers, 10, 12 base address, 63 battery, 52, 87, 89, 95, 100 BERR, 58,
EPC-5A Hardware & Software Reference Manual chassis, 13 Chipset term defined, G-3 CMOS RAM, 27, 52 CMOS Setup, 97 CMOS setup parameters, 52 COM1, 3, 26, 87 COM2, 3, 26, 41, 87 commander, 72 Configuration Byte functional definition of the, G-3 configuration options, 7 configuration registers, 77 connectors, 87 Conventional Memory term defined, G-3 CPU, 3 Ctrl+Alt+Del, 54, 78 Cylinders/Heads/Sectors (CHS) term defined, G-4 D D08, 61, 65 D16, 61, 62, 65, 73 D32, 61, 65 daisy chain, 57 daisy-chain lines, 10 da
Index F Fast Page Mode DRAMs term defined, G-5 Flash Boot Device term defined, G-5 Flash memory, 3 Flash Recovery term defined, G-5 Flash Update term defined, G-5 floating-point numbers, 62 floppy, 26 floppy diskette errors, 96, 97 front panel LEDs, 53 interrupt generator register, 65 interrupt mapping, B-1 Interrupt Request (IRQ) term defined, G-7 interrupts, 83 IRQ10 interrupt, 75 J J1 connector, 12, 57 J2 connector, 57 jumper, 7, 8, 10, 57 jumpers, 11, 12 term defined, G-7 K G general failure, 98 glob
EPC-5A Hardware & Software Reference Manual MEMORY PARITY INTERRUPT, 99 memory upgrades, 48, 91 message high register, 73 message interrupt, 74 message protocol, 73 message register, 72 message-based device, 69 model code, 70 modem, 3, 26 MODID, 57, 71 MODID jumper, 8 Module carrier, 19, 20, 21, 23, 24 module identification, 71 monitor, 25 mouse, 25, 26 MSGR interrupt, 73, 74 N Non-system disk error, 99 non-warranty service, 108 O Offset term defined, G-8 Operating System term defined, G-8 P P2, 54 page
Index servant, 72 service, 107 setup parameters, 52 setup screen, 25, 53 shadowing, 51 SIMMs, 48, 91 Single In-Line Memory Module (SIMM) term defined, G-11 slave, 53, 63, 65 slave accesses, 64 slave base, 72 slave boards, 10 slave enable, 71 slave memory, 63, 64 slave size, 70 Slot-1 controller, 8, 10, 57, 58 Slot-1 jumper, 7 speaker, 87, 89 specifications, 4, 91 status/ID, 65 status/ID value, 65 subplane, 8, 15, 16, 17, 18, 19, 20, 23 support, 107 Symmetrically Addressable SIMM term defined, G-11 SYSCLK, 5
EPC-5A Hardware & Software Reference Manual NOTES Page I-VI
