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ADC08060

8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter

General Description

The ADC08060 is a low-power, 8-bit, monolithic analog-to-

digital converter with an on-chip track-and-hold circuit. Opti-

mized for low cost, low power, small size and ease of use,

this product operates at conversion rates of 20 MSPS to 70

MSPS with outstanding dynamic performance over its full

operating range while consuming just 1.3 mW per MHz of

clock frequency. That’s just 78 mW of power at 60 MSPS.

Raising the PD pin puts the ADC08060 into a Power Down

mode where it consumes just 1 mW.

The unique architecture achieves 7.5 Effective Bits with

25 MHz input frequency. The excellent DC and AC charac-

teristics of this device, together with its low power consump-

tion and single +3V supply operation, make it ideally suited

for many imaging and communications applications, includ-

ing use in portable equipment. Furthermore, the ADC08060

is resistant to latch-up and the outputs are short-circuit proof.

The top and bottom of the ADC08060’s reference ladder are

available for connections, enabling a wide range of input

possibilities. The digital outputs are TTL/CMOS compatible

with a separate output power supply pin to support interfac-

ing with 3V or 2.5V logic. The digital inputs (CLK and PD) are

TTL/CMOS compatible.

The ADC08060 is offered in a 24-lead plastic package

(TSSOP) and is specified over the industrial temperature

range of −40˚C to +85˚C. An evaluation board is available to

assist in the easy evaluation of the ADC08060.

Features

n Single-ended input

n Internal sample-and-hold function

n Low voltage (single +3V) operation

n Small package

n Power-down feature

Key Specifications

n Resolution 8 bits

n Maximum sampling frequency 60 MSPS (min)

n DNL 0.4 LSB (typ)

n ENOB 7.5 bits (typ) at f

=25MHz

n THD −60 dB (typ)

n No missing codes Guaranteed

n Power Consumption

— Operating 1.3 mW/MSPS (typ)

— Power Down Mode 1 mW (typ)

Applications

n Digital imaging systems

n Communication systems

n Portable instrumentation

n Viterbi decoders

n Set-top boxes

Pin Configuration

20006201

November 2003

ADC08060 8-Bit, 60 MSPS, 1.3 mW/MSPS A/D Converter

Summary of content (19 pages)

PAGE 1
ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter General Description Features The ADC08060 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 20 MSPS to 70 MSPS with outstanding dynamic performance over its full operating range while consuming just 1.3 mW per MHz of clock frequency. That’s just 78 mW of power at 60 MSPS.
PAGE 2
ADC08060 Ordering Information ADC08060CIMT TSSOP ADC08060CIMTX TSSOP (tape and reel) ADC08060EVAL Evaluation Board Block Diagram 20006202 Pin Descriptions and Equivalent Circuits Pin No. Symbol 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information.
PAGE 3
Equivalent Circuit ADC08060 Pin Descriptions and Equivalent Circuits (Continued) Pin No. Symbol Description 23 PD Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins hold the last conversion result. 24 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. 13 thru 16 and 19 thru 22 D0–D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB.
PAGE 4
ADC08060 Absolute Maximum Ratings Soldering Temperature, Infrared, 10 seconds (Note 6) (Notes 1, 2) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA) −0.
PAGE 5
(Continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) CLK, PD DIGITAL INPUT CHARACTERISTICS IIL Logical Low Input Current CIN Logic Input Capacitance VIL = 0V, DR VD = VA = 2.
PAGE 6
ADC08060 Converter Electrical Characteristics (Continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Typical (Note 9) Limits (Note 9) Units (Limits) DC Input 76 96 mW (max) fIN = 10 MHz, VIN = FS − 3 dB, PD = Low 88 mW CLK Low, PD = Hi 0.
PAGE 7
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless other- INL INL vs. Temperature 20006208 20006214 INL vs. Supply Voltage INL vs. Sample Rate 20006210 20006215 DNL DNL vs. Temperature 20006209 20006217 7 www.national.
PAGE 8
ADC08060 Typical Performance Characteristics VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated (Continued) DNL vs. Supply Voltage DNL vs. Sample Rate 20006211 20006218 SNR vs. Temperature SNR vs. Supply Voltage 20006220 20006221 SNR vs. Sample Rate SNR vs. Input Frequency 20006212 www.national.
PAGE 9
SNR vs. Clock Duty Cycle Distortion vs. Temperature 20006224 20006225 Distortion vs. Supply Voltage Distortion vs. Sample Rate 20006226 20006213 Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle 20006228 20006229 9 www.national.
PAGE 10
ADC08060 Typical Performance Characteristics VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated (Continued) SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage 20006238 20006230 SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Clock Duty Cycle 20006216 20006240 SINAD/ENOB vs. Input Frequency Power Consumption vs. Sample Rate 20006239 www.national.
PAGE 11
Spectral Response @ fIN = 10.1 MHz Spectral Response @ fIN = 25 MHz 20006244 20006245 Intermodulation Distortion (IMD) 20006242 11 www.national.
PAGE 12
ADC08060 how well an a.c. signal riding upon the power supply is rejected and is here defined as: Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes low. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as noise at the output.
PAGE 13
ADC08060 Timing Diagram 20006231 FIGURE 1. ADC08060 Timing Diagram convert as long as the clock signal is present. The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode, where the output pins hold the last conversion before the PD pin went high and the device consumes just 1 mW. Functional Description The ADC08060 uses a new, unique architecture that achieves over 7.4 effective bits at input frequencies up to 30 MHz.
PAGE 14
ADC08060 Applications Information (Continued) 20006232 FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the reference voltage can vary too much for some applications. changed to suit your reference voltage needs, or the divider can be replaced with potentiometers for precise settings. The bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion is 0V.
PAGE 15
ADC08060 Applications Information (Continued) 20006233 FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. VRT should always be at least 1.0V more positive than VRB to minimize noise. VRM (pin 9) is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float. the analog input pin.
PAGE 16
ADC08060 Applications Information (Continued) 20006234 FIGURE 4. The input amplifier should incorporate some gain for best performance (see text). The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material.
PAGE 17
ADC08060 clock pin as seen from the clock source. Typical tPD is about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes (Continued) 4.0 THE DIGITAL INPUT PINS The ADC08060 has two digital input pins: The PD pin and the Clock pin. 4.1 The PD Pin The Power Down (PD) pin, when high, puts the ADC08060 into a low power mode where power consumption is reduced to 1 mW. Output data is valid and accurate about 1 microsecond after the PD pin is brought low.
PAGE 18
ADC08060 Applications Information basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC08060. Such practice may lead to conversion inaccuracies and even to device damage.
PAGE 19
ADC08060 8-Bit, 60 MSPS, 1.3 mW/MSPS A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.