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TL/H/11086

ADC08061/ADC08062

500 ns A/D Converter with S/H Function and Input Multiplexer

November 1995

ADC08061/ADC08062

500 ns A/D Converter with S/H Function

and Input Multiplexer

General Description

Using a patented multi-step A/D conversion technique, the

8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns

(typ) conversion time, internal sample-and-hold (S/H), and

dissipate only 125 mW of power. The ADC08062 has a two-

channel multiplexer. The ADC08061/2 family performs an

8-bit conversion using a 2-bit voltage estimator that gener-

ates the 2 MSBs and two low-resolution (3-bit) flashes that

generate the 6 LSBs.

Input track-and-hold circuitry eliminates the need for an ex-

ternal sample-and-hold. The ADC08061/2 family performs

accurate conversions of full-scale input signals that have a

frequency range of DC to 300 kHz (full-power bandwidth)

without need of an external S/H.

The digital interface has been designed to ease connection

to microprocessors and allows the parts to be I/O or memo-

ry mapped.

Key Specifications

Resolution 8 bits

Conversion Time 560 ns max (WR-RD Mode)

Full Power Bandwidth 300 kHz

Throughput rate 1.5 MHz

Power Dissipation 100 mW max

Total Unadjusted Error

(/2 LSB and

1 LSB

Features

1 or 2 input channels

No external clock required

Analog input voltage range from GND to V

Overflow output available for cascading (ADC08061)

ADC08061 pin-compatible with the industry standard

ADC0820

Applications

Mobile telecommunications

Hard disk drives

Instrumentation

High-speed data acquisition systems

Block Diagram

*ADC08061 TL/H/11086–1

**ADC08062

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A.

http://www.national.com

Summary of content (16 pages)

PAGE 1
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer General Description Key Specifications Using a patented multi-step A/D conversion technique, the 8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns (typ) conversion time, internal sample-and-hold (S/H), and dissipate only 125 mW of power. The ADC08062 has a twochannel multiplexer.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Lead Temperature (Note 5) J Package (Soldering, 10 sec.) N Package (Soldering, 10 sec.) WM Package (Vapor Phase, 60 sec.) WM Package (Infrared, 15 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
PAGE 3
AC Electrical Characteristics The following specifications apply for V a e 5V, tr e tf e 10 ns, VREF a e 5V, VREFb e 0V unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 4
DC Electrical Characteristics The following specifications apply for V a e 5V unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. Symbol VIH VIL IIH IIL VOH VOL IO Parameter Logic ‘‘1’’ Input Voltage Logic ‘‘0’’ Input Voltage Logic ‘‘1’’ Input Current Logic ‘‘0’’ Input Current Logic ‘‘1’’ Output Voltage Logic ‘‘0’’ Output Voltage TRI-STATE Output Current Limits (Note 8) Units (Limit) V a e 5.5V Mode Pin 3.
PAGE 5
Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
PAGE 6
TRI-STATE Test Circuits and Waveforms t1H t1H, CL e 10 pF TL/H/11086–2 TL/H/11086 – 4 tr e 10 ns t0H t0H, CL e 10 pF TL/H/11086 – 5 TL/H/11086–3 tr e 10 ns Timing Diagrams TL/H/11086 – 6 FIGURE 1. RD Mode (Mode Pin is Low) http://www.national.
PAGE 7
Timing Diagrams (Continued) TL/H/11086 – 7 FIGURE 2a. WR-RD Mode (Mode Pin is High and tRD s tINTL) TL/H/11086 – 8 FIGURE 2b. WR-RD Mode (Mode Pin is High and tRD l tINTL) 7 http://www.national.
PAGE 8
Timing Diagrams (Continued) TL/H/11086 – 9 FIGURE 3. WR-RD Mode (Mode Pin is High) Reduced Interface System Connection (CS e RD e 0) TL/H/11086 – 10 FIGURE 4. RD Mode (Pipeline Operation) (Mode Pin is Low and tRDW must be between 200 ns and 400 ns) http://www.national.
PAGE 9
Typical Performance Characteristics tCRD vs Temperature Linearity Error vs Reference Voltage Offset Error vs Reference Voltage Supply Current vs Temperature Logic Threshold vs Temperature Output Current vs Temperature TL/H/11086 – 24 Connection Diagrams TL/H/11086 – 14 TL/H/11086 – 15 Dual-In-Line and Wide-Body Small-Outline Packages J20A, N20A or M20B Dual-In-Line and Wide-Body Small-Outline Packages N20A or M20B Ordering Information Industrial (b40§ C s TA s 85§ C) Package ADC08061BIN, ADC08
PAGE 10
Pin Description VREFb VIN, VIN1 –8 These are analog inputs. The input range is GND – 50 mV s VINPUT s V a a 50 mV. The ADC08061 has a single input (VIN) and the ADC08062 has a two-channel multiplexer (VIN1 – 2). DB0 – DB7 TRI-STATE data outputsÐbit 0 (LSB) through bit 7 (MSB). WR/RDY WR-RD Mode (Logic high applied to MODE pin) WR: With CS low, the conversion is started on the falling edge of WR. The digital result will be strobed into the output latch at the end of conversion (see Figures 2a, 2b, and 3 ).
PAGE 11
Application Information voltage across it. Tap points are found between all of the resistors in both the MSB and LSB Ladders. Through the Comparator Multiplexer these tap points can be connected, in groups of eight, to the eight comparators shown at the right of Figure 5 . This function provides the necessary reference voltages to the comparators during each flash conversion. The six comparators, seven-resistor string (estimator DAC), and Estimator Decoder at the left of Figure 5 form the Voltage Estimator.
PAGE 12
Application Information (Continued) A conversion begins with the Voltage Estimator comparing the analog input signal against the six tap voltages on the estimator DAC. The estimator decoder then selects one of the groups of tap points along the MSB Ladder. These eight tap points are then connected to the eight flash comparators.
PAGE 13
Application Information (Continued) shows the input code needed to select a given channel. The multiplexer address is latched when received but the multiplexer channel is updated after the completion of the current conversion. 4.0 ANALOG INPUT AND SOURCE IMPEDANCE The ADC08061/2’s analog input circuitry includes an analog switch with an ‘‘on’’ resistance of 70X and capacitance of 1.4 pF and 12 pF (see Figure 6 ).
PAGE 14
Application Information (Continued) External Reference 2.5V Full-Scale (Standard Application) Power Supply as Reference Input Not Referred to GND TL/H/11086 – 21 TL/H/11086–20 TL/H/11086 – 22 Note: Bypass capacitors consist of a 0.1 mF ceramic in parallel with a 10 mF bead tantalum. FIGURE 7. Analog Input Options *Signal source driving VIN( b ) must be capable of sinking 5 mA. TL/H/11086 – 23 Note the multiple bypass capacitors on the reference and power supply pins.
PAGE 15
Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number ADC08061CMJ or ADC08061CMJ/883,5962 NS Package Number J20A Wide-Body Small-Outline Package (M) Order Number ADC08061BIWM, ADC08061CIWM, ADC08062BIWM or ADC08062CIWM NS Package Number M20B 15 http://www.national.
PAGE 16
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer Physical Dimensions inches (millimeters) (Continued) Dual-In-Line Package (N) Order Number ADC08061BIN, ADC08061CIN, ADC08062BIN or ADC08062CIN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.