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ADC08161

500 ns A/D Converter with S/H Function and 2.5V

Bandgap Reference

General Description

Using a patented multi-step A/D conversion technique, the

8-bit ADC08161 CMOS A/D converter offers 500 ns conver-

sion time, internal sample-and-hold (S/H), a 2.5V bandgap

reference, and dissipates only 100 mW of power. The

ADC08161 performs an 8-bit conversion with a 2-bit voltage

estimator that generates the 2 MSBs and two low-resolution

(3-bit) flashes that generate the 6 LBSs.

Input signals are tracked and held by the input sampling cir-

cuitry, eliminating the need for an external sample-and-hold.

The ADC08161 can perform accurate conversions of

full-scale input signals at frequencies from DC to typically

more than 300 kHz (full power bandwidth) without the need

of an external sample-and-hold (S/H).

For ease of interface to microprocessors, this part has been

designed to appear as a memory location or I/O port without

the need for external interfacing logic.

Key Specifications

n Resolution: 8 Bits

n Conversion time (t

CONV

): 560 ns max (WR -RD Mode)

n Full power bandwidth: 300 kHz (typ)

n Throughput rate: 1.5 MHz min

n Power dissipation: 100 mW max

n Total unadjusted error:

⁄

LSB and

1 LSB max

Features

n No external clock required

n Analog input voltage range from GND to V

n 2.5V bandgap reference

Applications

n Mobile telecommunications

n Hard-disk drives

n Instrumentation

n High-speed data acquisition systems

Block Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

DS011149-1

November 1995

ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference

Summary of content (16 pages)

PAGE 1
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference General Description Key Specifications Using a patented multi-step A/D conversion technique, the 8-bit ADC08161 CMOS A/D converter offers 500 ns conversion time, internal sample-and-hold (S/H), a 2.5V bandgap reference, and dissipates only 100 mW of power. The ADC08161 performs an 8-bit conversion with a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that generate the 6 LBSs.
PAGE 2
Absolute Maximum Ratings (Notes 1, WM Package (Vapor Phase, 60 sec.) WM Package (Infrared, 15 sec.) Storage Temperature ESD Susceptibility (Note 6) 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
PAGE 3
Converter Characteristics (Continued) The following specifications apply for RD Mode, V+ = 5V, VREF+ = 5V, and VREF− = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions THD Total Harmonic Distortion S/N Signal-to-Noise Ratio VIN = 4.85 Vp-p fIN = 20 Hz to 20 kHz VIN = 4.85 Vp-p Intermodulation Distortion fIN = 20 Hz to 20 kHz VIN = 4.85 Vp-p IMD Typical Limits Units (Note 7) (Note 8) (Limit) 0.
PAGE 4
AC Electrical Characteristics (Continued) The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
PAGE 5
DC Electrical Characteristics (Continued) The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions ADC08161BIN, ADC08161CIN, ADC08161BIWM, ADC08161CIWM ISINK Output Sink Current VOUT = 5V DB0–DB7, OFL , INT , RDY CS = WR = RD = 0 Units (Limit) Typical Limit (Note 7) (Note 8) 24 7 mA (min) 11.
PAGE 6
Bandgap Reference Electrical Characteristics (Continued) Note 11: Off-channel leakage current is measured on the on-channel selection. TRI-STATE Test Circuit and Waveforms t1H, CL = 10 pF t1H DS011149-2 DS011149-4 tr = 10 ns t0H, CL = 10 pF t0H DS011149-5 tr = 10 ns DS011149-3 DS011149-6 FIGURE 1. RD Mode (Mode Pin is Low) www.national.
PAGE 7
TRI-STATE Test Circuit and Waveforms (Continued) DS011149-7 FIGURE 2. WR -RD Mode with tRD ≤ tINTL (Mode Pin is High) DS011149-8 FIGURE 3. WR -RD Mode with tRD > tINTL (Mode Pin is High) 7 www.national.
PAGE 8
TRI-STATE Test Circuit and Waveforms (Continued) DS011149-9 FIGURE 4. WR -RD Mode Reduced Interface System Connection with CS = RD = 0 (Mode Pin is High) DS011149-10 FIGURE 5. RD Mode (Pipeline Operation); tRDW must be between 200 ns and 400 ns. (Mode Pin is Low) Typical Performance Characteristics tCRD vs Temperature Linearity Error vs Reference Voltage Offset Error vs Reference Voltage DS011149-23 DS011149-24 www.national.
PAGE 9
Typical Performance Characteristics Supply Current vs Temperature (Continued) Logic Threshold vs Temperature Reference Output Voltage vs Temperature DS011149-26 DS011149-28 DS011149-27 Output Current vs Temperature DS011149-29 Connection Diagram Dual-In-Line and Wide-Body Small-Outline Packages DS011149-14 See NS Package Number N20A or M20A Pin Description Ordering Information Industrial (−40˚C ≤ TA ≤ 85˚C) VIN Package ADC08161BIN, ADC08161CIN N20A ADC08161BIWM, ADC08161CIWM M20B This is
PAGE 10
Pin Description (Continued) WR /RDY WR -RD Mode (Logic high applied to MODE pin) WR : With CS low, the conversion is started on the rising edge of WR . The digital result will be strobed into the output latch at the end of conversion (Figures 2, 3, 4). RD Mode (Logic low applied to MODE pin) RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS and returns high at the end of conversion.
PAGE 11
Application Information DS011149-17 FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture Ladders. Through the Comparator Multiplexer these tap points can be connected, in groups of eight, to the eight comparators shown at the right of Figure 6. This function provides the necessary reference voltages to the comparators during each flash conversion. The six comparators, seven-resistor string (estimator DAC), and Estimator Decoder at the left of Figure 6 form the Voltage Estimator.
PAGE 12
Application Information tween the rising edge of CS (after the end of a conversion) and the start of the next conversion (by pulling RD low). The RDY output goes low after the falling edge of CS and goes high at the end-of-conversion. It can be used to signal a processor that the converter is busy or serve as a system Transfer Acknowledge signal. (Continued) points are then connected to the eight flash comparators.
PAGE 13
Application Information ternal S/H. In a non-sampling converter, regardless of its speed, the input must remain stable to at least 1⁄2 LSB throughout the conversion process if full accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled and held stationary during the conversion. The ADC08161 is suitable for DSP-based systems because of the direct control of the S/H through the WR signal.
PAGE 14
Application Information Internal Reference 2.5V Full-Scale (Standard Application) (Continued) Power Supply as Reference Input Not Referred to GND DS011149-20 DS011149-21 DS011149-19 *Signal source driving VIN(−) must be capable of sinking 5 mA. Note: Bypass capacitors consist of a 0.1 µF ceramic in parallel with a 10 µF bead tantalum, unless otherwise specified. FIGURE 8. Analog Input Options DS011149-22 FIGURE 9. Typical Connection.
PAGE 15
Physical Dimensions inches (millimeters) unless otherwise noted Wide-Body Small-Outline Order Number ADC08161BIWM or ADC08161CIWM NS Package Number M20B Dual-In-Line Order Number ADC08161BIN or ADC08161CIN NS Package Number N20A 15 www.national.
PAGE 16
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1.