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TL/H/5501

ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function

February 1995

ADC0820 8-Bit High Speed mP Compatible

A/D Converter with Track/Hold Function

General Description

By using a half-flash conversion technique, the 8-bit

ADC0820 CMOS A/D offers a 1.5 ms conversion time and

dissipates only 75 mW of power. The half-flash technique

consists of 32 comparators, a most significant 4-bit ADC

and a least significant 4-bit ADC.

The input to the ADC0820 is tracked and held by the input

sampling circuitry eliminating the need for an external sam-

ple-and-hold for signals moving at less than 100 mV/ms.

For ease of interface to microprocessors, the ADC0820 has

been designed to appear as a memory location or I/O port

without the need for external interfacing logic.

Key Specifications

Resolution 8 Bits

Conversion Time 2.5 ms Max (RD Mode)

1.5 ms Max (WR-RD Mode)

Input signals with slew rate of 100 mV/ms converted

without external sample-and-hold to 8 bits

Low Power 75 mW Max

Total Unadjusted Error

(/2 LSB and

1 LSB

Features

Built-in track-and-hold function

No missing codes

No external clocking

Single supplyÐ5 V

Easy interface to all microprocessors, or operates

stand-alone

Latched TRI-STATE

output

Logic inputs and outputs meet both MOS and T

L volt-

age level specifications

Operates ratiometrically or with any reference value

equal to or less than V

0V to 5V analog input voltage range with single 5V

supply

No zero or full-scale adjust required

Overflow output available for cascading

0.3

standard width 20-pin DIP

20-pin molded chip carrier package

20-pin small outline package

20-pin shrink small outline package (SSOP)

Connection and Functional Diagrams

Dual-In-Line, Small Outline and

SSOP Packages

TL/H/5501–1

Top View

Molded Chip Carrier

Package

TL/H/5501–33

TL/H/5501–2

FIGURE 1

See Ordering Information

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (20 pages)

PAGE 1
ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function General Description Features By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 ms conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Lead Temp. (Soldering, 10 sec.) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) Surface Mount Package Vapor Phase (60 sec.) Infrared (15 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
PAGE 3
DC Electrical Characteristics The following specifications apply for VCC e 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. ADC0820BCN, ADC0820CCN ADC0820BCV, ADC0820CCV ADC0820BCWM, ADC0820CCWM ADC0820CCMSA, ADC0820CIWM ADC0820CCJ Parameter Conditions Tested Design Limit Limit (Note 7) (Note 8) Typ (Note 6) VIN(1), Logical ‘‘1’’ Input Voltage VCC e 5.25V VIN(0), Logical ‘‘0’’ Input Voltage VCC e 4.
PAGE 4
AC Electrical Characteristics (Continued) The following specifications apply for VCC e 5V, tr e tf e 20 ns, VREF( a ) e 5V, VREF(b) e 0V and TA e 25§ C unless otherwise specified.
PAGE 5
Timing Diagrams Note: On power-up the state of INT can be high or low. TL/H/5501 – 7 FIGURE 2. RD Mode (Pin 7 is Low) TL/H/5501 – 8 FIGURE 3a. WR-RD Mode (Pin 7 is High and tRDktI) TL/H/5501 – 10 FIGURE 4. WR-RD Mode (Pin 7 is High) Stand-Alone Operation TL/H/5501 – 9 FIGURE 3b.
PAGE 6
Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage Conversion Time (RD Mode) vs Temperature Power Supply Current vs Temperature (not including reference ladder) Accuracy vs tWR Accuracy vs tRD Accuracy vs tp Accuracy vs VREF [VREF e VREF ( a )bVREF (b)] tI, Internal Time Delay vs Temperature Output Current vs Temperature *1 LSB e VREF 256 TL/H/5501 – 11 6
PAGE 7
Description of Pin Functions Pin Name 1 2 3 4 5 6 VIN DB0 DB1 DB2 DB3 WR/RDY 7 Mode 8 RD Pin Name Function Analog input; range e GNDsVINsVCC TRI-STATE data outputÐbit 0 (LSB) TRI-STATE data outputÐbit 1 TRI-STATE data outputÐbit 2 TRI-STATE data outputÐbit 3 WR-RD Mode WR: With CS low, the conversion is started on the falling edge of WR.
PAGE 8
1.0 Functional Description (Continued) The actual circuitry used in the ADC0820 is a simple but important expansion of the basic comparator described above. By adding a second capacitor and another set of switches to the input (Figure 6 ), the scheme can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch on each capacitor (Z switches) are closed in the zeroing cycle.
PAGE 9
Detailed Block Diagram TL/H/5501 – 15 FIGURE 7 9
PAGE 10
1.0 Functional Description (Continued) When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from zeroing to comparison mode (Figure 8 ). When WR is returned high after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle.
PAGE 11
1.0 Functional Description (Continued) TL/H/5501 – 20 Note: MS means most significant LS means least significant FIGURE 8. Operating Sequence (WR-RD Mode) 2.2 INPUT CURRENT Due to the unique conversion techniques employed by the ADC0820, the analog input behaves somewhat differently than in conventional devices. The A/D’s sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. The equivalent input circuit of the ADC0820 is shown in Figure 10a .
PAGE 12
2.0 Analog Considerations (Continued) External Reference 2.5V Full-Scale Power Supply as Reference TL/H/5501–21 Input Not Referred to GND TL/H/5501 – 22 TL/H/5501 – 23 FIGURE 9. Analog Input Options TL/H/5501 – 25 TL/H/5501–24 FIGURE 10a FIGURE 10b 2.3 INPUT FILTERING It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/D’s performance in most cases.
PAGE 13
3.
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3.
PAGE 15
Digital Waveform Recorder TL/H/5501 – 32 3.
PAGE 16
Ordering Information Part Number Total Unadjusted Error Package g (/2 LSB V20AÐMolded Chip Carrier M20BÐWide Body Small Outline N20AÐMolded DIP ADC0820BCV ADC0820BCWM ADC0820BCN ADC0820CCJ ADC0820CCMSA ADC0820CCV ADC0820CCWM ADC0820CIWM ADC0820CCN g 1 LSB J20AÐCerdip MSA20Ð Shrink Small Outline Package V20AÐMolded Chip Carrier M20BÐWide Body Small Outline M20BÐWide Body Small Outline N20AÐMolded DIP 16 Temperature Range 0§ C to a 70§ C 0§ C to a 70§ C 0§ C to a 70§ C b 40§ C to a 85§ C 0§ C to a 7
PAGE 17
PAGE 18
Physical Dimensions inches (millimeters) Hermetic Dual-In-Line Package (J) Order Number ADC0820CCJ NS Package Number J20A SO Package (M) Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM NS Package Number M20B 18
PAGE 19
Physical Dimensions inches (millimeters) (Continued) Shrink Small Outline Package (SSOP) Order Number ADC0820CCMSA NS Package Number MSA20 Molded Dual-In-Line Package (N) Order Number ADC0820BCN or ADC0820CCN NS Package Number N20A 19
PAGE 20
ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function Physical Dimensions inches (millimeters) (Continued) Molded Chip Carrier Package (V) Order Number ADC0820BCV or ADC0820CCV NS Package Number V20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.