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TL/H/5016

ADC0844/ADC0848 8-Bit mP Compatible A/D Converters with Multiplexer Options

December 1994

ADC0844/ADC0848 8-Bit mP Compatible A/D Converters

with Multiplexer Options

General Description

The ADC0844 and ADC0848 are CMOS 8-bit successive

approximation A/D converters with versatile analog input

multiplexers. The 4-channel or 8-channel multiplexers can

be software configured for single-ended, differential or

pseudo-differential modes of operation.

The differential mode provides low frequency input common

mode rejection and allows offsetting the analog range of the

converter. In addition, the A/D’s reference can be adjusted

enabling the conversion of reduced analog ranges with 8-bit

resolution.

The A/Ds are designed to operate from the control bus of a

wide variety of microprocessors. TRI-STATE

output latch-

es that directly drive the data bus permit the A/Ds to be

configured as memory locations or I/O devices to the micro-

processor with no interface logic necessary.

Features

Easy interface to all microprocessors

Operates ratiometrically or with 5 V

voltage reference

No zero or full-scale adjust required

4-channel or 8-channel multiplexer with address logic

Internal clock

0V to 5V input range with single 5V power supply

0.3

standard width 20-pin or 24-pin DIP

28 Pin Molded Chip Carrier Package

Key Specifications

Resolution 8 Bits

Total Unadjusted Error

(/2 LSB and

1 LSB

Single Supply 5 V

Low Power 15 mW

Conversion Time 40 ms

Block and Connection Diagrams

*ADC0848 shown in

DIP Package

CH5-CH8 not included

on the ADC0844

TL/H/5016–1

Dual-In-Line Package

TL/H/5016–2

Top View

Dual-In-Line Package

TL/H/5016–30

Top View

Molded Chip Carrier Package

TL/H/5016–29

Top View

See Ordering Information

TRI-STATE

is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (20 pages)

PAGE 1
ADC0844/ADC0848 8-Bit mP Compatible A/D Converters with Multiplexer Options General Description Features The ADC0844 and ADC0848 are CMOS 8-bit successive approximation A/D converters with versatile analog input multiplexers. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential or pseudo-differential modes of operation. The differential mode provides low frequency input common mode rejection and allows offsetting the analog range of the converter.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Lead Temperature (Soldering, 10 seconds) Dual-In-Line Package (Plastic) Dual-In-Line Package (Ceramic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) 6.5V Voltage Logic Control Inputs At Other Inputs and Outputs b 0.3V to a 15V b 0.3V to VCC a 0.
PAGE 3
Electrical Characteristics The following specifications apply for VCC e 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e Tj e 25§ C. (Continued) Parameter ADC0844BCJ ADC0844CCJ ADC0848BCJ ADC0848CCJ Conditions Typ (Note 5) Tested Limit (Note 6) b 0.
PAGE 4
Note 9: For VIN ( b ) t VIN ( a ) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale.
PAGE 5
TRI-STATE Test Circuits and Waveforms t1H t1H, CL e 10 pF TL/H/5016 – 4 TL/H/5016 – 5 tr e 20 ns t0H t0H, CL e 10 pF TL/H/5016 – 7 tr e 20 ns TL/H/5016 – 6 Leakage Current Test Circuit TL/H/5016 – 8 5
PAGE 6
Timing Diagrams Programming New Channel Configuration and Starting a Conversion TL/H/5016 – 9 Note 1: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR. Note 2: MA stands for MUX address.
PAGE 7
TL/H/5016 – 11 ADC0848 Functional Block Diagram 7
PAGE 8
Functional Description ferred to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the conversion result on the data lines (DB0-DB7). The ADC0844 and ADC0848 contain a 4-channel and 8channel analog input multiplexer (MUX) respectively. Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended. These modes are discussed in the Applications Information Section.
PAGE 9
Applications Information (Continued) ended, or pseudo-differential. Figure 1 shows the three modes using the 4-channel MUX ADC0844. The eight inputs of the ADC0848 can also be configured in any of the three modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CH1 with CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable.
PAGE 10
Applications Information (Continued) ‘‘ a ’’ input and then the ‘‘b’’ inputs is (/2 of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: 4.0 OPTIONAL ADJUSTMENTS 4.1 Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a zero offset can be done.
PAGE 11
Applications Information (Continued) The full-scale adjustment should be made [with the proper VIN (b) voltage applied] by forcing a voltage to the VIN ( a ) input which is given by: Ð VMIN e the low end (the offset zero) of the analog range. (Both are ground referenced.) The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. For an example see the Zero-Shift and Span Adjust circuit below.
PAGE 12
Applications Information (Continued) Differential Voltage Input 9-Bit A/D TL/H/5016 – 19 Span Adjust 0VsVINs3V TL/H/5016 – 20 Protecting the Input TL/H/5016 – 21 Diodes are 1N914 12
PAGE 13
Applications Information (Continued) High Accuracy Comparators TL/H/5016 – 22 DO e all 1s if VIN( a ) l VIN( b ) DO e all 0s if VIN( a ) k VIN( b ) Operating with Automotive Ratiometric Transducers TL/H/5016 – 23 *VIN( b ) e 0.
PAGE 14
Applications Information (Continued) A Stand Alone Circuit TL/H/5016 – 25 Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848. Start a Conversion without Updating the Channel Configuration TL/H/5016 – 26 CS # WR will update the channel configuration and start a conversion. CS # RD will read the conversion data and start a new conversion without updating the channel configuration. Waiting for the end of this conversion is not necessary.
PAGE 15
Applications Information (Continued) ADC0844ÐINS8039 Interface TL/H/5016 – 27 0000 04 10 0010 B9 FF 0012 0014 0016 B8 20 89 FF 23 00 0018 001A 14 50 23 02 001C 001D 18 14 50 SAMPLE PROGRAM FOR ADC0844ÐINS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS ORG 0H JMP BEGIN ;START PROGRAM AT ADDR 10 ORG 10H ;MAIN PROGRAM BEGIN: MOV R1,Ý0FFH ;LOAD R1 WITH A UNUSED ADDR ;LOCATION MOV R0,Ý20H ;A/D DATA ADDRESS ORL P1,Ý0FFH ;SET PORT 1 OUTPUTS HIGH MOV A,00H ;LOAD THE ACC WITH A/D MUX DATA
PAGE 16
Applications Information (Continued) I/O Interface to NSC800 TL/H/5016 – 28 SAMPLE PROGRAM FOR ADC0848ÐNSC800 INTERFACE 0008 000F 001F 3C00 0000Ê 0004Ê 0008Ê 000AÊ 000CÊ 000FÊ 0012Ê 08 09 0A 0B 0C 0D 0E 0F 0E 1F 06 16 21 0000Ê 11 003C ED A3 0014Ê EB 0015Ê 0017Ê 0018Ê 001BÊ 3E 0F 3D C2 0013Ê ED A2 001DÊ 001EÊ EB C2 000EÊ NCONV DEL CS ADDTA EQU EQU EQU EQU 16 15 1FH 003CH MUXDTA: DB DB LD LD LD LD OUTI 08H,09H,0AH,0BH 0CH,0DH,0EH,0FH C,CS B,NCONV HL,MUXDTA DE,ADDTA EX DE,HL LD DEC JP INI A,
PAGE 17
Ordering Information Temperature Range Total Unadjusted Error g (/2 LSB g 1 LSB ADC0844BCN ADC0844CCN 0§ C to a 70§ C ADC0848BCN ADC0848CCN ADC0844BCJ ADC0844CCJ b 40§ C to a 85§ C ADC0848BCJ ADC0848CCJ ADC0848BCV ADC0848CCV 17 MUX Channels Package Outline 4 N20A Molded Dip 8 N24C Molded Dip 4 J20A Cerdip 8 J24F Cerdip 8 V28A Molded Chip Carrier
PAGE 18
Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) NS Package Number J20A Cavity Dual-In-Line Package (J) NS Package Number J24F 18
PAGE 19
Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) NS Package Number N20A Molded Dual-In-Line Package (N) NS Package Number N24C 19
PAGE 20
ADC0844/ADC0848 8-Bit mP Compatible A/D Converters with Multiplexer Options Physical Dimensions inches (millimeters) (Continued) Molded Chip Carrier Package (V) NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.