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ADC08L060

8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D

Converter with Internal Sample-and-Hold

General Description

The ADC08L060 is a low-power, 8-bit, monolithic analog-to-

digital converter with an on-chip track-and-hold circuit. Opti-

mized for low cost, low power, small size and ease of use,

this product operates at conversion rates of 10 MSPS to

60 MSPS while consuming just 0.65 mW per MHz of clock

frequency, or 39 mW at 60 MSPS. Raising the PD pin puts

the ADC08L060 into a Power Down mode where it con-

sumes about 1 mW.

The unique architecture achieves 7.6 Effective Bits. The

ADC08L060 is resistant to latch-up and the outputs are

short-circuit proof. The top and bottom of the ADC08L060s

reference ladder are available for connections, enabling a

wide range of input possibilities. The digital outputs are

TTL/CMOS compatible with a separate output power supply

pin to support interfacing with 1.8V to 3V logic. The digital

inputs (CLK and PD) are TTL/CMOS compatible.

The ADC08L060 is offered in a 24-lead plastic package

(TSSOP) and is specified over the industrial temperature

range of −40˚C to +85˚C. An evaluation board is available to

assist in the evaluation of the ADC08L060.

Features

n Single-ended input

n Internal sample-and-hold function

n Low voltage (single +3V) operation

n Small package

n Power-down feature

Key Specifications

n Resolution 8 bits

n Conversion rate 60 MSPS

n DNL

0.25 LSB (typ)

n INL +0.5/−0.2 LSB (typ)

n SNR (10.1 MHz) 48 dB (typ)

n ENOB (10.1 MHz) 7.6 bits (typ)

n THD (10.1 MHz) −57 dB (typ)

n Latency 5 Clock Cycles

n No missing codes Guaranteed

n Power Consumption

— Operating 0.65 mW/MSPS (typ)

— Power Down Mode 1.0 mW (typ)

Applications

n Digital Imaging

n Set-top boxes

n Portable Instrumentation

n Communication Systems

n X-ray imaging

n Viterbi decoders

Pin Configuration

20041701

July 2004

ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal

Sample-and-Hold

Summary of content (18 pages)

PAGE 1
ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold General Description Features The ADC08L060 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS.
PAGE 2
ADC08L060 Ordering Information Order Number (−40˚C ≤ TA ≤ +85˚C) Package ADC08L060CIMT TSSOP ADC08L060CIMTX TSSOP (tape and reel) ADC08L060EVAL Evaluation Board Block Diagram 20041702 www.national.
PAGE 3
ADC08L060 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 9 VRM Mid-point of the reference ladder.
PAGE 4
ADC08L060 Absolute Maximum Ratings Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VA Supply Voltage (VA) Driver Supply Voltage (VDR) Reference Voltage (VRT, VRB) VA to AGND CLK, PD Voltage Range −0.05V to (VA + 0.
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(Continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8) Symbol Parameter IIL Logical Low Input Current CIN Logic Input Capacitance Conditions VIL = 0V, VDR = VA = 2.7V Typical (Note 9) Limits (Note 9) Units (Limits) −50 nA 3 pF DIGITAL OUTPUT CHARACTERISTICS VOH High Level Output Voltage VA = VDR = 2.7V, IOH = −400 µA 2.
PAGE 6
ADC08L060 Converter Electrical Characteristics (Continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8) Symbol Parameter Typical (Note 9) Conditions Limits (Note 9) Units (Limits) DYNAMIC PERFORMANCE tOD Output Delay Sampling (Aperture) Delay tAJ Aperture Jitter ns (min) 9.4 ns (max) 7.1 CLK Rise to Acquisition of Data 2.
PAGE 7
APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes high. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period.
PAGE 8
ADC08L060 Timing Diagram 20041710 FIGURE 1. ADC08L060 Timing Diagram Typical Performance Characteristics VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless other- wise stated INL INL vs. Temperature 20041753 20041712 INL vs. Supply Voltage, VA INL vs. Sample Rate 20041713 www.national.
PAGE 9
INL vs. Clock Duty Cycle DNL 20041754 20041715 DNL vs. Temperature DNL vs. Supply Voltage, VA 20041717 20041718 DNL vs. Sample Rate DNL vs. Clock Duty Cycle 20041719 20041720 9 www.national.
PAGE 10
ADC08L060 Typical Performance Characteristics VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated (Continued) SNR, SINAD and SFDR vs. Temperature SNR, SINAD and SFDR vs. Supply Voltage, VA 20041721 20041722 SNR, SINAD and SFDR vs. Sample Rate SNR, SINAD and SFDR vs. Input Frequency 20041723 20041724 SNR, SINAD and SFDR vs. Clock Duty Cycle Distortion vs. Temperature 20041725 www.national.
PAGE 11
Distortion vs. Supply Voltage, VA Distortion vs. Sample Rate 20041727 20041728 Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle 20041729 20041730 Power Consumption (Active) vs. Sample Rate (fIN = d.c.) Power Consumption (Active) vs. Sample Rate (fIN = d.c.) 20041731 20041738 11 www.national.
PAGE 12
ADC08L060 Typical Performance Characteristics VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated (Continued) Power Consumption (Active) vs. Sample Rate (fIN = 1 MHz) Power Consumption (Active) vs. Sample Rate (fIN = 1 MHz) 20041739 20041740 Spectral Response @ fIN = 10 MHz Spectral Response @ fIN = 29 MHz 20041755 20041757 Spectral Response @ fIN = 75 MHz Spectral Response @ fIN = 98.9 MHz 20041756 www.national.
PAGE 13
The ADC08L060 uses a unique architecture that achieves over 7 effective bits at input frequencies up to and beyond Nyquist. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. Applications Information 1.
PAGE 14
ADC08L060 Applications Information (Continued) 20041733 FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. 2.0 THE ANALOG INPUT The analog input of the ADC08L060 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of the analog input causes current spikes that result in voltage spikes at the analog input pin.
PAGE 15
ADC08L060 Applications Information (Continued) 20041734 FIGURE 4. The input amplifier should incorporate some gain for best performance (see text). 3.0 POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power pins, with a 0.
PAGE 16
ADC08L060 Applications Information from each other. Of course, locate all analog circuitry and traces over the analog power plane and the digital circuitry and traces over the digital power plane. To minimize RFI/ EMI, give proper attention to any lines crossing the analog/ digital power plane boundary. Noise performance is also enhanced by driving a single gate with each ADC output pin and locating the gate as close as possible to the ADC output.
PAGE 17
more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC08L060.
PAGE 18
ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.