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TL/H/5675

ADC1001 10-Bit mP Compatible A/D Converter

December 1994

ADC1001 10-Bit mP Compatible A/D Converter

General Description

The ADC1001 is a CMOS, 10-bit successive approximation

A/D converter. The 20-pin ADC1001 is pin compatible with

the ADC0801 8-bit A/D family. The 10-bit data word is read

in two 8-bit bytes, formatted left justified and high byte first.

The six least significant bits of the second byte are set to

zero, as is proper for a 16-bit word.

Differential inputs provide low frequency input common

mode rejection and allow offsetting the analog range of the

converter. In addition, the reference input can be adjusted

enabling the conversion of reduced analog ranges with 10-

bit resolution.

Features

ADC1001 is pin compatible with ADC0801 series 8-bit

A/D converters

Compatible with NSC800 and 8080 mP derivativesÐno

interfacing logic needed

Easily interfaced to 6800 mP derivatives with minimal

external logic

Differential analog voltage inputs

Logic inputs and outputs meet both MOS and TTL volt-

age level specifications

Works with 2.5V (LM336) voltage reference

On-chip clock generator

0V to 5V analog input voltage range with single 5V sup-

ply

Operates ratiometrically or with 5 V

, 2.5 V

, or ana-

log span adjusted voltage reference

0.3

standard width 20-pin DIP package

Key Specifications

Resolution 10 bits

Linearity error

1 LSB

Conversion time 200mS

Connection Diagram

ADC1001 (for an 8-bit data bus)

Dual-In-Line Package

TL/H/5675–11

Top View

Ordering Information

Temperature Range 0

Cto

Order Number ADC1001CCJ-1 ADC1001CCJ

Package Outline J20A J20A

TRI-STATE

is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (8 pages)

PAGE 1
ADC1001 10-Bit mP Compatible A/D Converter General Description The ADC1001 is a CMOS, 10-bit successive approximation A/D converter. The 20-pin ADC1001 is pin compatible with the ADC0801 8-bit A/D family. The 10-bit data word is read in two 8-bit bytes, formatted left justified and high byte first. The six least significant bits of the second byte are set to zero, as is proper for a 16-bit word.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Range ADC1001CCJ b 40§ C s TA s a 85§ C ADC1001CCJ-1 Range of VCC Supply Voltage (VCC) (Note 3) 6.5V b 0.3V to a 18V Logic Control Inputs Voltage at Other Inputs and Outputs b0.3V to (VCC a 0.
PAGE 3
DC Electrical Characteristics The following specifications apply for VCC e 5 VDC and TMINsTAs TMAX, unless otherwise specified. Symbol Parameter Conditions MIn Typ Max Units 15 VDC 0.8 VDC 1 mADC CONTROL INPUTS [Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical ‘‘1’’ Input Voltage (Except CLK IN) VCC e 5.25 VDC VIN (0) Logical ‘‘0’’ Input Voltage (Except CLK IN) VCC e 4.
PAGE 4
Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance CLK IN Schmitt Trip Levels vs Supply Voltage Output Current vs Temperature TL/H/5675 – 2 TRI-STATE Test Circuits and Waveforms t1H, CL e 10 pF TL/H/5675–3 TL/H/5675 – 4 tr e 20 ns t0H, CL e 10 pF TL/H/5675 – 6 tr e 20 ns TL/H/5675–5 4
PAGE 5
Timing Diagrams TL/H/5675 – 7 Output Enable and Reset INTR TL/H/5675 – 8 Note: All timing is measured from the 50% voltage points.
PAGE 6
Functional Description clocked in, which allows the conversion process to continue. If the set signal were to still be present, this reset pulse would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F.
PAGE 7
Typical Application TL/H/5675 – 1 Block Diagram Note 1: CS shown twice for clarity. Note 2: SAR e Successive Approximation Register.
PAGE 8
ADC1001 10-Bit mP Compatible A/D Converter Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) (Side Brazed) Order Number ADC1001CCJ or ADC1001CCJ-1 NS Package Number J20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.