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ADC10065

10-Bit 65 MSPS 3V A/D Converter

General Description

The ADC10065 is a monolithic CMOS analog-to-digital con-

verter capable of converting analog input signals into 10-bit

digital words at 65 Megasamples per second (MSPS). This

converter uses a differential, pipeline architecture with digital

error correction and an on-chip sample-and-hold circuit to

provide a complete conversion solution, and to minimize

power consumption, while providing excellent dynamic per-

formance. A unique sample-and-hold stage yields a full-

power bandwidth of 400 MHz. Operating on a single 3.0V

power supply, this device consumes just 68.4 mW at

65 MSPS, including the reference current. The Standby

feature reduces power consumption to just 14 .1 mW.

The differential inputs provide a full scale selectable input

swing of 2.0 V

P-P

, 1.5 V

P-P

, 1.0 V

P-P

, with the possibility of a

single-ended input. Full use of the differential input is recom-

mended for optimum performance. An internal +1.2V preci-

sion bandgap reference is used to set the ADC full-scale

range, and also allows the user to supply a buffered refer-

enced voltage for those applications requiring increased ac-

curacy. The output data format is 10-bit offset binary, or two’s

complement.

This device is available in the 28-lead TSSOP package and

will operate over the industrial temperature range of −40˚C to

+85˚C.

Features

n Single +3.0V operation

n Selectable 2.0 V

P-P

, 1.5 V

P-P

, or 1.0 V

P-P

full-scale input

swing

n 400 MHz −3 dB input bandwidth

n Low power consumption

n Standby mode

n On-chip reference and sample-and-hold amplifier

n Offset binary or two’s complement data format

n Separate adjustable output driver supply to

accommodate 2.5V and 3.3V logic families

n 28-pin TSSOP package

Key Specifications

n Resolution 10 Bits

n Conversion Rate 65 MSPS

n Full Power Bandwidth 400 MHz

n DNL

0.3 LSB (typ)

n SNR (f

= 11 MHz) 59.6 dB (typ)

n SFDR (f

= 11 MHz) −80 dB (typ)

n Data Latency 6 Clock Cycles

n Supply Voltage +3.0V

n Power Consumption, 65 MHz 68.4 mW

Applications

n Ultrasound and Imaging

n Instrumentation

n Cellular Based Stations/Communications Receivers

n Sonar/Radar

n xDSL

n Wireless Local Loops

n Data Acquisition Systems

n DSP Front Ends

Connection Diagram

20077901

November 2004

ADC10065 10-Bit 65 MSPS 3V A/D Converter

Summary of content (19 pages)

PAGE 1
ADC10065 10-Bit 65 MSPS 3V A/D Converter General Description Features The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance.
PAGE 2
ADC10065 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) NS Package ADC10065CIMT 28 Pin TSSOP ADC10065CIMTX 28 Pin TSSOP Tape & Reel Block Diagram 20077902 www.national.
PAGE 3
ADC10065 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O Inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. 12 VIN− 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. 6 VREF Reference input. This pin should be bypassed to VSSA with a 0.1 µF monolithic capacitor. VREF is 1.
PAGE 4
ADC10065 Pin Descriptions and Equivalent Circuits Pin No. Symbol 16–20, 23–27 D0–D9 Equivalent Circuit (Continued) Description Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. ANALOG POWER 2, 9, 10 VDDA Positive analog supply pins. These pins should be connected to a quiet 3.0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.7 µF capacitor should also be used in parallel.
PAGE 5
Operating Ratings (Notes 1, 2) Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDDA (Supply Voltage) VDDA, VDDIO Package Dissipation at T = 25˚C 1.20V ≤ 100 mV |VSSA–VSSIO| NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired.
PAGE 6
ADC10065 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C Symbol Parameter Conditions Min Typ Max Units 0.
PAGE 7
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C Symbol Parameter Conditions Min (Note 12) Typ (Note 12) Max (Note 12) Units 65 MHz (min) CLK, DF, STBY, SENSE fCLK1 Maximum Clock Frequency fCLK2 Minimum Clock Frequency 20 MHz tCH Clock High Time 7.
PAGE 8
ADC10065 PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay.
PAGE 9
ADC10065 Timing Diagram 20077909 FIGURE 1. Clock and Data Timing Diagram Transfer Characteristics 20077910 FIGURE 2. Input vs. Output Transfer Characteristic 9 www.national.
PAGE 10
ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. DNL DNL vs. fCLK 20077912 20077915 DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature 20077913 20077916 INL INL vs. fCLK 20077917 20077914 www.national.
PAGE 11
INL vs. Clock Duty Cycle SNR vs. VDDIO 20077918 20077919 SNR vs. VDDA SNR vs. fCLK 20077920 20077921 INL vs. Temperature SNR vs. Clock Duty Cycle 20077922 20077923 11 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle.
PAGE 12
ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) SNR vs. Temperature THD vs. VDDA 20077924 20077925 THD vs. VDDIO THD vs. fCLK 20077926 20077927 SNR vs. IRS THD vs. IRS 20077928 www.national.
PAGE 13
SINAD vs. VDDA SINAD vs. VDDIO 20077930 20077931 THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20077932 20077933 THD vs. Temperature SINAD vs. Temperature 20077934 20077935 13 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle.
PAGE 14
ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) SINAD vs. fCLK SFDR vs. VDDIO 20077936 20077937 SINAD vs. IRS SFDR vs. fCLK 20077939 20077938 SFDR vs. VDDA SFDR vs. IRS 20077940 www.national.
PAGE 15
Spectral Response @ 11 MHz Input SFDR vs. Clock Duty Cycle 20077942 20077943 Spectral Response @ 32 MHz Input SFDR vs. Temperature 20077944 20077945 Power Consumption vs. fCLK 20077946 15 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle.
PAGE 16
ADC10065 Functional Description The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode, each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin (pin 5), and be centered around VCM and be 180˚ out of phase with each other.
PAGE 17
charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance.
PAGE 18
ADC10065 Applications Information (Continued) 20077950 FIGURE 6. A Simple Application Using a Single Ended Driving Source www.national.
PAGE 19
ADC10065 10-Bit 65 MSPS 3V A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead TSSOP Package Ordering Number ADC10065CIMT NS Package Number MTC28 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com.