User Manual

Functional Description
The ADC10065 uses a pipeline architecture and has error
correction circuitry to help ensure maximum performance.
Differential analog input signals are digitized to 10 bits. In
differential mode, each analog input signal should have a
peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depend-
ing on the state of the IRS pin (pin 5), and be centered
around V
CM
and be 180˚ out of phase with each other. If
single ended operation is desired, V
IN
- may be tied to the
V
COM
pin (pin 4). A single ended input signal may then be
applied to V
IN
+, and should have an average value in the
range of V
CM
. The signal amplitude should be 2.0V, 1.5V or
1.0V peak-to-peak, depending on the state or the IRS pin
(pin 5).
Applications Information
1.0 ANALOG INPUTS
The ADC10065 has two analog signal inputs, V
IN
+ and V
IN
−.
These two pins form a differential input pair. There is one
common mode pin V
COM
that may be used to set the com-
mon mode input voltage.
1.1 REFERENCE PINS
The ADC10065 is designed to operate with a 1.2V reference,
but performs well with reference voltages in the range of
0.8V to 2.0V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC10065. It is very im-
portant that all grounds associated with the reference volt-
age and the input signal make connection to the analog
ground plane at a single point to minimize the effects of
noise currents in the ground path. The three Reference
Bypass Pins V
REF
,V
REFT
and V
REFB
, are made available for
bypass purposes only. These pins should each be bypassed
to ground with a 0.1 µF capacitor. DO NOT LOAD these pins.
1.2 V
COM
PIN
This pin supplies a voltage for possible use to set the com-
mon mode input voltage. This pin may also be connected to
V
IN
-, so that V
IN
+ may be used as a single ended input. This
pin should be bypassed with at least a 0.1 uF capacitor.
1.3 SIGNAL INPUTS
The signal inputs are V
IN
+ and V
IN
−. The input signal ampli-
tude is defined as V
IN
+−V
IN
− and is represented schemati-
cally in Figure 3:
A single ended input signal is shown in Figure 4.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 18Ω series resistors at each of the signal
inputs with a 25 pF capacitor across the inputs, as can be
seen in Figure 5. These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The two 18Ω resistors and the 25 pF capaci-
tors form a low-pass filter with a -3 dB frequency of 177 Mhz.
1.4 CLK PIN
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 20 MHz to 65 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚. The CLK signal also drives
an internal state machine. If the CLK is interrupted, or its
frequency is too low, the charge on internal capacitors can
dissipate to the point where the accuracy of the output data
will degrade. This is what limits the lowest sample rate to
20 MSPS. The duty cycle of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC10065 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle, performance is typically maintained over a clock
duty cycle range of 40% to 60%.
1.5 STBY PIN
The STBY pin, when high, holds the ADC10065 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 15 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down.
1.6 DF PIN
The DF pin, when high, forces the ADC10065 to output the
2’s complement data format. When DF is tied low, the output
format is offset binary.
1.7 IRS PIN
The IRS (Input Range Select) pin defines the input signal
amplitude that will produce a full scale output. The table
below describes the function of the IRS pin.
20077947
FIGURE 3. Input Voltage Waveforms for a 2V
P-P
differential Input
20077948
FIGURE 4. Input Voltage Waveform for a 2V
P-P
Single
Ended Input
ADC10065
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