User Manual

AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
SSA
=V
SSIO
= 0V, V
DDA
= +3.0V, V
DDIO
= +2.5V, V
IN
=
2V
P-P
, STBY = 0V, V
REF
= 1.20V, (Externally Supplied) f
CLK
= 65 MHz, 50% Duty Cycle, C
L
= 10 pF/pin. Boldface limits ap-
ply for T
A
=T
MIN
to T
MAX
: all other limits T
A
= 25˚C
Symbol Parameter Conditions Min
(Note 12)
Typ
(Note
12)
Max
(Note
12)
Units
CLK, DF, STBY, SENSE
f
CLK
1 Maximum Clock Frequency 65 MHz (min)
f
CLK
2 Minimum Clock Frequency 20 MHz
t
CH
Clock High Time 7.69 ns
t
CL
Clock Low Time 7.69 ns
t
CONV
Conversion Latency 6 Cycles
t
OD
Data Output Delay after a Rising
Clock Edge
T = 25˚C 2 3.4 5 ns
16ns
t
AD
Aperture Delay 1 ns
t
AJ
Aperture Jitter 2 ps (RMS)
Over Range Recovery Time
Differential V
IN
step from
±
3V to 0V to get
accurate conversion
1 Clock Cycle
t
STBY
Standby Mode Exit Cycle 20 Cycles
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = V
SSA
=V
SSIO
= 0V, unless otherwise specified.
Note 3: When the voltage at any pin exceeds the power supplies (V
IN
<
V
SSA
or V
IN
>
V
DDA
,V
DDIO
), the current at that pin should be limited to 25 mA. The 50 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
J
max, the
junction-to-ambient thermal resistance (θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula P
D
MAX=(T
J
max − T
A
)/θ
JA
. In the 28-pin
TSSOP, θ
JA
is 96˚C/W, so P
D
MAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of
this device under normal operation will typically be about 68.6 mW. The values for maximum power dissipation listed above will be reached only when the ADC10065
is operated in a severe fault condition.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage
this device. However, input errors will be generated if the input goes above V
DDA
or V
DDIO
and below V
SSA
or V
SSIO
.
Note 7: VCOM is a typical value, measured at room temperature. It is not guaranteed by test.
20077907
Note 8: To guarantee accuracy, it is required that |V
DDA
–V
DDIO
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for 2 V
P-P
differential input, the 10-bit LSB is 1.95 mV.
Note 10: Typical figures are at T
A
=T
J
= 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
IL
= 0.4V for a falling edge, and V
IH
= 2.4V for a rising edge.
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
Note 14: I
DDIO
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
V
DR
, and the rate at which the outputs are switching (which is signal dependent). I
DR
=V
DR
x(C
0
xf
0
+C
1
xf
1
+C
2
+f
2
+....C
11
xf
11
) where V
DR
is the output driver
supply voltage, C
n
is the total load capacitance on the output pin, and f
n
is the average frequency at which the pin is toggling.
Note 15: Power consumption includes output driver power. (f
IN
= 0 MHz).
Note 16: The input bandwidth is limited using a 10 pF capacitor between V
IN
−
and V
IN
+
.
Note 17: V
COM
is a typical value, measured at room temperature, and is not guaranteed by test.
ADC10065
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