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ADC11DL066

Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D

Converter w/Internal Reference

General Description

The ADC11DL066 is a dual, low power monolithic CMOS

analog-to-digital converter capable of converting analog in-

put signals into 11-bit digital words at 66 Megasamples per

second (MSPS), minimum. This converter uses a differential,

pipeline architecture with digital error correction and an on-

chip sample-and-hold circuit to minimize die size and power

consumption while providing excellent dynamic performance

and a 450 MHz Full Power Bandwidth. Operating on a single

3.3V power supply, the ADC11DL066 achieves 10.3 effective

bits and consumes just 686 mW at 66 MSPS, including the

reference current. The Power Down feature reduces power

consumption to 75 mW.

The differential inputs provide a full scale differential input

swing equal to 2 times V

REF

with the possibility of a single-

ended input. Full use of the differential input is recom-

mended for optimum performance. The digital outputs from

the two ADCs are available on separate 11-bit buses with an

output data format choice of offset binary or two’s comple-

ment.

To ease interfacing to lower voltage systems, the digital

output driver power pins of the ADC11DL066 can be con-

nected to a separate supply voltage in the range of 2.4V to

the digital supply voltage.

This device is available in the 64-lead TQFP package and

will operate over the industrial temperature range of −40˚C to

+85˚C. An evaluation board is available to ease the evalua-

tion process.

Features

n Single +3.3V supply operation

n Internal sample-and-hold

n Outputs 2.4V to 3.3V compatible

n Power down mode

n On-chip reference

Key Specifications

n Resolution 11 Bits

n DNL

0.25 LSB (typ)

n SNR (f

= 10 MHz) 64 dB (typ)

n SFDR (f

= 10 MHz) 80 dB (typ)

n Data Latency 6 Clock Cycles

n Power Consumption

— Operating 686 mW (typ)

— Power Down 75 mW (typ)

Applications

n Ultrasound and Imaging

n Instrumentation

n Communications Receivers

n Sonar/Radar

n xDSL

n Cable Modems

n DSP Front Ends

Connection Diagram

20077301

20040326

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

March 2004

ADC11DL066 Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference

Summary of content (23 pages)

PAGE 1
ADC11DL066 Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference General Description Features The ADC11DL066 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 11-bit digital words at 66 Megasamples per second (MSPS), minimum.
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ADC11DL066 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC11DL066CIVS 64 Pin TQFP Block Diagram 20077302 www.national.
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Pin No. Symbol Equivalent Circuit Description ANALOG I/O Differential analog Inputs. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VCM. The negative input pins may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. 15 2 VINA+ VINB+ 16 1 VINA− VINB− 7 VREF Reference input. This pin should be bypassed to AGND with a 0.
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ADC11DL066 Pin Descriptions and Equivalent Circuits Pin No. Symbol 25–29 34–39 DA0–DA10 Equivalent Circuit (Continued) Description Digital data output pins that make up the 11-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA10 and DB10 are the MSBs of the output words. Output levels are TTL/CMOS compatible. 43–47 52–57 DB0–DB10 ANALOG POWER 9, 18, 19, 62, 63 VA 3, 8, 10, 17, 20, 61, 64 AGND Positive analog supply pins.
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Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) VA, VD, VDR Package Dissipation at TA = 25˚C −0.05V to (VD + 0.05V) Analog Input Pins 0V to (VA − 0.5V) VCM 0.5V to 1.8V ≤100mV |AGND–DGND| ± 25 mA ± 50 mA Package Input Current (Note 3) 0.8V to 1.5V CLK, PD, OE −0.3V to (VA or VD +0.
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ADC11DL066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
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Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, INT/EXT REF pin = 3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) 2.0 V (min) 1.
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ADC11DL066 AC Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, INT/EXT REF pin = 3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 3 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter tAJ Aperture Jitter tHOLD Conditions Typical (Note 10) Limits (Note 10) Units (Limits) 1.
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APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. OFFSET ERROR is the difference between the two input voltages (VIN+–VIN−) required to cause a transition from code 1023 to 1024. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output.
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ADC11DL066 Timing Diagram 20077309 Output Timing Transfer Characteristic 20077310 FIGURE 1. Transfer Characteristic www.national.
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VA = VD = +3.3V, VDR = +2.5V, fCLK = 66 MHz, fIN = 10 MHz DNL DNL vs. fCLK 20077318 20077319 DNL vs. Clock Duty Cycle DNL vs. VDR 20077320 20077321 DNL vs. Temperature INL 20077322 20077360 11 www.national.
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ADC11DL066 Typical Performance Characteristics VA = VD = +3.3V, VDR = +2.5V, fCLK = 66 MHz, fIN = 10 MHz unless otherwise stated (Continued) INL vs. fCLK INL vs. Clock Duty Cycle 20077324 20077325 INL vs. VDR INL vs. Temperature 20077326 20077327 SNR, SINAD, SFDR vs. fCLK SNR, SINAD, SFDR vs. CLOCK DUTY CYCLE 20077328 www.national.
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SNR, SINAD, SFDR vs. VREF SNR, SINAD, SFDR vs. VCM 20077331 20077332 SNR, SINAD, SFDR vs. VDR SNR, SINAD, SFDR vs. Temperature 20077333 20077334 Distortion vs. FCLK Distortion vs. Clock Duty Cycle 20077336 20077337 13 www.national.com ADC11DL066 Typical Performance Characteristics VA = VD = +3.3V, VDR = +2.
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ADC11DL066 Typical Performance Characteristics VA = VD = +3.3V, VDR = +2.5V, fCLK = 66 MHz, fIN = 10 MHz unless otherwise stated (Continued) Distortion vs. VREF Distortion vs. VCM 20077338 20077339 Distortion vs. VDR Distortion vs. Temperature 20077340 20077341 tOD vs. VDR SPECTRAL PLOT, FIN = 1 MHz 20077343 www.national.
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SPECTRAL PLOT, FIN = 10 MHz SPECTRAL PLOT, FIN = 33 MHz 20077362 20077363 15 www.national.com ADC11DL066 Typical Performance Characteristics VA = VD = +3.3V, VDR = +2.
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ADC11DL066 Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. DO NOT LOAD these pins. Loading any of these pins may result in performance degradation. Functional Description Operating on a single +3.3V supply, the ADC11DL066 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 11 bits.
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TABLE 1. Input to Output Relationship – Differential Input (Continued) VIN+ VIN− Binary Output 2’s Complement Output VCM − VREF / 2 VCM + VREF / 2 000 0000 0000 100 0000 0000 VCM − VREF / 4 VCM + VREF / 4 010 0000 0000 110 0000 0000 VCM VCM 100 0000 0000 000 0000 0000 VCM − VCM + VREF / 4 VREF / 4 110 0000 0000 010 0000 0000 VCM − VCM + VREF / 2 VREF / 2 111 1111 1111 011 1111 1111 20077311 TABLE 2. Input to Output Relationship – Single-Ended Input FIGURE 2.
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ADC11DL066 Applications Information The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC11DL066 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 43% to 57% at 66 MSPS.
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output data. The result could be an apparent reduction in dynamic performance. (Continued) Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance.
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ADC11DL066 Applications Information (Continued) 20077314 FIGURE 5. Differential Drive Circuit of Figure 4 Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families.
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ADC11DL066 Applications Information (Continued) 20077316 FIGURE 6. Example of a Suitable Layout Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g.
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ADC11DL066 Applications Information The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC11DL066, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. (Continued) Using an inadequate amplifier to drive the analog input. As explained in Section 1.
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inches (millimeters) 64-Lead TQFP Package Ordering Number ADC11DL066CIVS NS Package Number VEC64A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.