Manual

Applications Information (Continued)
For single frequency sine waves the full scale error in LSB
can be described as approximately
E
FS
=2048(1-sin(90˚ + dev))
Where dev is the angular difference in degrees between the
two signals having a 180˚ relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
For differential operation, each analog input pin of the differ-
ential pair should have a peak-to-peak voltage equal to the
reference voltage, V
REF
, be 180 degrees out of phase with
each other and be centered around V
CM
.
1.3.1 Single-Ended Operation
Performance with differential input signals is better than with
single-ended signals. For this reason, single-ended opera-
tion is not recommended. However, if single ended-operation
is required and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to
the d.c. mid point voltage of the driven input. The peak-to-
peak differential input signal at the driven input pin should be
twice the reference voltage to maximize SNR and SINAD
performance (Figure 2b). For example, set V
REF
to 0.5V,
bias V
IN
− to 1.5V and drive V
IN
+ with a signal range of 1.0V
to 2.0V.
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
when maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC11DL066.
TABLE 1. Input to Output Relationship – Differential
Input
V
IN
+
V
IN
−
Binary Output
2’s Complement
Output
V
CM
−
V
REF
/2
V
CM
+
V
REF/2
000 0000 0000 100 0000 0000
V
CM
−
V
REF/4
V
CM
+
V
REF
/4
010 0000 0000 110 0000 0000
V
CM
V
CM
100 0000 0000 000 0000 0000
V
CM
+
V
REF
/4
V
CM
−
V
REF
/4
110 0000 0000 010 0000 0000
V
CM
+
V
REF
/2
V
CM
−
V
REF
/2
111 1111 1111 011 1111 1111
TABLE 2. Input to Output Relationship – Single-Ended
Input
V
IN
+
V
IN
−
Binary Output
2’s Complement
Output
V
CM
−
V
REF
V
CM
000 0000 0000 100 0000 0000
V
CM
−
V
REF
/2
V
CM
010 0000 0000 110 0000 0000
V
CM
V
CM
100 0000 0000 000 0000 0000
V
CM
+
V
REF
/2
V
CM
110 0000 0000 010 0000 0000
V
CM
+
V
REF
V
CM
111 1111 1111 011 1111 1111
1.3.2 Driving the Analog Inputs
The V
IN
+ and the V
IN
− inputs of the ADC11DL066 consist of
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog input. Do not attempt to filter
out these pulses. Rather, use amplifiers to drive the
ADC11DL066 input pins that are able to react to these
pluses and settle before the switch opens and another
sample is taken. The LMH6702 LMH6628, LMH6622 and the
LMH6655 are good amplifiers for driving the ADC11DL066.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 4
and Figure 5 . These components should be placed close to
the ADC inputs because the input pins of the ADC is the
most sensitive part of the system and this is the last oppor-
tunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wide-
band undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency to
maintain a linear delay response.
20077311
FIGURE 2. Expected Input Signal Range
20077312
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
ADC11DL066
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