Manual

Applications Information (Continued)
A single-ended to differential conversion circuit is shown in
Figure 5. Table 3 gives resistor values for that circuit to
provide input signals in a range of 1.0V
±
0.5V at each of the
differential input pins of the ADC11DL066.
TABLE 3. Resistor Values for Circuit of Figure 5
SIGNAL
RANGE
R1 R2 R3 R4 R5, R6
0 - 0.25V open 0Ω 124Ω 1500Ω 1000Ω
0 - 0.5V 0Ω openΩ 499Ω 1500Ω 499Ω
±
0.25V 100Ω 698Ω 100Ω 698Ω 499Ω
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
CM
, should be in the
range of 0.5V to 1.8V and be a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than one Volt below the V
A
supply voltage. The nominal V
CM
should generally be about
1.0V, but V
RM
or V
RN
can be used as a V
CM
source as long
as no d.c. current is drawn from either of these pins. See
Section 1.2
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB, OF, INT/EXT REF and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 15 MHz to 75 MHz with rise and fall times of 2
ns or less. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the ac-
curacy of the output data will degrade. This is what limits the
lowest sample rate to 15 MSPS.
The clock line should be terminated at its source in the
characteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on
setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, as shown in Figure 4, such that
the resistor value is equal to the characteristic impedance of
the clock line and the capacitor value is
where t
PD
is the signal propagation rate down the clock line,
"L" is the line length and Z
O
is the characteristic impedance
of the clock line. This termination should be as close as
possible to the ADC clock pin but beyond it as seen from the
clock source. Typical t
PD
is about 150 ps/inch (60 ps/cm) on
FR-4 board material. The units of "L" and t
PD
should be the
same (inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC11DL066 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 43% to 57% at 66 MSPS.
2.2 OEA, OEB
The OEA and OEB pins, when high, put the output pins of
their respective converters into a high impedance state.
When either of these pin is low, the corresponding outputs
are in the active state. The ADC11DL066 will continue to
convert whether these pins are high or low, but the output
can not be read while the pin is high.
Since ADC noise increases with increased output capaci-
tance at the digital output pins, do not use the TRI-STATE
outputs of the ADC11DL066 to drive a bus. Rather, each
output pin should be located close to and drive a single
digital input pin. To further reduce ADC noise, a 100 Ω
resistor in series with each ADC digital output pin, located
close to their respective pins, should be added to the circuit.
2.3 PD
The PD pin, when high, holds the ADC11DL066 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 66MHz clock and 40mW if the clock is stopped when
PD is high. The output data pins are undefined and the data
in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 4, 5, 6, 12, 13 and 14 and
is about 500 µs with the recommended components on the
V
RP
,V
RM
and V
RN
reference bypass pins. These capacitors
loose their charge in the Power Down mode and must be
recharged by on-chip circuitry before conversions can be
accurate. Smaller capacitor values allow slightly faster re-
covery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
2.4 OF
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high. While the sense of this pin may be changed "on the fly,"
doing this is not recommended as the output data could be
erroneous for a few clock cycles after this change is made.
2.5 INT/EXT REF
The INT/EXT REF pin determines whether the internal ref-
erence or an external reference voltage is used. With this pin
at a logic low, the internal 1.0V reference is in use. With this
pin at a logic high an external reference must be applied to
the V
REF
pin, which should then be bypassed to ground.
There is no need to bypass the V
REF
pin when the internal
reference is used. There is no access to the internal refer-
ence voltage, but its value is approximately equal to V
RP
−
V
RN
.
3.0 OUTPUTS
The ADC11DL066 has 11 TTL/CMOS compatible Data Out-
put pins. Valid data is present at these outputs while the OE
and PD pins are low. While the t
OD
time provides information
about output timing, a simple way to capture a valid output is
to latch the data on the falling edge of the conversion clock
(pin 10).
ADC11DL066
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