ADC11L066 11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold General Description Features The ADC11L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 11-bit digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS.
ADC11L066 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC11L066CIVY 32 Pin LQFP ADC11L066CIVYX 32 Pin LQFP Tape and Reel Block Diagram 20050702 www.national.
ADC11L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ 3 VIN− 1 VREF 31 VRP 32 VRM 30 VRN Analog signal Input pins. With a 1.0V reference voltage the differential input signal level is 2.0 VP-P. The VIN- pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. VREF is 1.
ADC11L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol 15–19, 22–27 D0–D10 Equivalent Circuit (Continued) Description Digital data output pins that make up the 11-bit conversion results. D0 is the LSB, while D10 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.
Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) VA, VD, VDR Package Dissipation at TA = 25˚C −0.05V to (VD + 0.05V) VIN Input −0V to (VA − 0.5V) VCM 0.5V to (VA - 1.5V) ≤100 mV |AGND–DGND| ± 25 mA ± 50 mA Package Input Current (Note 3) 0.8V to 1.5V CLK, PD, OE −0.3V to VA or VD +0.
ADC11L066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) 62.8 dB (min) 63.4 dB (min) 62.
ADC11L066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter fIN = 10 MHz, Differential VIN = −0.5 dBFS 2nd Harm Typical (Note 10) Conditions 85˚C 25˚C fIN = 25 MHz, Differential VIN = −0.
ADC11L066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions fIN = 10 MHz, Differential VIN = −0.
ADC11L066 AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2/.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
ADC11L066 AC Electrical Characteristics (Continued) Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....
ADC11L066 Timing Diagram 20050709 Output Timing Transfer Characteristic 20050710 FIGURE 1. Transfer Characteristic 11 www.national.
ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. DNL DNL vs. fCLK 200507E6 20050791 DNL vs. Clock Duty Cycle DNL vs. Temperature 20050793 20050792 INL INL vs. fCLK 200507E7 www.national.
INL vs. Clock Duty Cycle INL vs. Temperature 20050796 20050795 SNR vs. VA SNR vs. VDR 20050797 20050798 SNR vs. VCM SNR vs. fCLK 200507B2 200507B1 13 www.national.com ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SNR vs. Clock Duty Cycle SNR vs. VREF 200507B3 200507B4 SNR vs. Temperature THD vs. VA 200507B5 200507B6 THD vs. VDR THD vs. VCM 200507B7 www.national.
THD vs. fCLK THD vs. Clock Duty Cycle 200507B9 200507C1 THD vs. VREF THD vs. Temperature 200507C3 200507C2 SINAD vs. VA SINAD vs. VDR 200507C5 200507C4 15 www.national.com ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SINAD vs. VCM SINAD vs. fCLK 200507C7 200507C6 SINAD vs. Clock Duty Cycle SINAD vs. VREF 200507C8 200507C9 SINAD vs. Temperature SFDR vs. VA 200507D1 www.national.
SFDR vs. VDR SFDR vs. VCM 200507D4 200507D3 SFDR vs. fCLK SFDR vs. Clock Duty Cycle 200507D6 200507D5 SFDR vs. VREF SFDR vs. Temperature 200507D8 200507D7 17 www.national.com ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) Power Consumption vs. fCLK tOD vs. VDR 200507D9 200507E1 Spectral Response @ 10 MHz Input Spectral Response @ 25MHz Input 200507E4 200507E8 Spectral Response @ 50 MHz Input Spectral Response @ 75 MHz Input 200507E9 www.national.
Spectral Response @ 150 MHz Input Spectral Response @ 100 MHz Input 200507J2 200507J1 Spectral Response @ 240 MHz Input 200507E5 19 www.national.com ADC11L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC11L066 1.1 Analog Inputs Functional Description The ADC11L066 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There is one reference input pin, VREF. Operating on a single +3.3V supply, the ADC11L066 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 11 bits.
Relationship–Differential Input and Table 2. Input to Output Relationship–Single-Ended Input indicate the input to output relationship of the ADC11L066. (Continued) The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency (sine wave) inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion. 1.3.
ADC11L066 Applications Information Since ADC noise increases with increased output capacitance at the digital output pins, do use the TRI-STATE outputs of the ADC11L066 to drive a bus. Rather, each output pin should be located close to and drive a single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output pin, located close to their respective pins, should be added to the circuit. See Section 3.0. (Continued) 2.
ADC11L066 Applications Information (Continued) 20050713 FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer 20050714 FIGURE 5. Differential Drive Circuit of Figure 4 23 www.national.
ADC11L066 Applications Information (Continued) 20050715 FIGURE 6. Driving the Signal Inputs with a Transformer exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC11L066’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance.
This is because of the skin effect. Total surface area is more important than is total ground plane volume. (Continued) weight will have little effect upon the logic-generated noise. 20050716 FIGURE 7. Example of a Suitable Layout Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether.
ADC11L066 Applications Information Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. (Continued) pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g.
inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC11L066CIVY NS Package Number VBE32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
