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TL/H/11354

ADC12H030/ADC12H032/ADC12H034/ADC12H038,

ADC12030/ADC12032/ADC12034/ADC12038

Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

January 1995

ADC12H030/ADC12H032/ADC12H034/ADC12H038,

ADC12030/ADC12032/ADC12034/ADC12038

Self-Calibrating 12-Bit Plus Sign Serial I/O

A/D Converters with MUX and Sample/Hold

General Description

The ADC12030, and ADC12H030 families are 12-bit plus

sign successive approximation A/D converters with serial

I/O and configurable input multiplexers. The ADC12032/

ADC12H032, ADC12034/ADC12H034 and ADC12038/

ADC12H038 have 2, 4 and 8 channel multiplexers, respec-

tively. The differential multiplexer outputs and A/D inputs

are available on the MUXOUT1, MUXOUT2, A/DIN1 and

A/DIN2 pins. The ADC12030/ADC12H030 has a two chan-

nel multiplexer with the multiplexer outputs and A/D inputs

internally connected. The ADC12030 family is tested with a

5 MHz clock, while the ADC12H030 family is tested with an

8 MHz clock. On request, these A/Ds go through a self

calibration process that adjusts linearity, zero and full-scale

errors to less than

1 LSB each.

The analog inputs can be configured to operate in various

combinations of single-ended, differential, or pseudo-differ-

ential modes. A fully differential unipolar analog input range

(0V to

5V) can be accommodated with a single

5V sup-

ply. In the differential modes, valid outputs are obtained

even when the negative inputs are greater than the positive

because of the 12-bit plus sign output data format.

The serial I/O is configured to comply with the NSC

MICROWIRE

. For complementary voltage references see

the LM4040, LM4041 or LM9140.

Applications

Medical instruments

Process control systems

Test equipment

Features

Serial I/O (MICROWIRE Compatible)

2, 4, or 8 channel differential or single-ended

multiplexer

Analog input sample/hold function

Power down mode

Variable resolution and conversion rate

Programmable acquisition time

Variable digital output word length and format

No zero or full scale adjustment required

Fully tested and guaranteed with a 4.096V reference

0V to 5V analog input range with single 5V power

supply

No Missing Codes over temperature

Key Specifications

Resolution 12-bit plus sign

12-bit plus sign conversion time

Ð ADC12H030 family 5.5 ms (max)

Ð ADC12030 family 8.8 ms (max)

12-bit plus sign throughput time

Ð ADC12H030 family 8.6 ms (max)

Ð ADC12030 family 14 ms (max)

Integral linearity error

1 LSB (max)

Single supply 5V

10%

Power dissipation 33 mW (max)

Ð Power down 100 mW (typ)

ADC12038 Simplified Block Diagram

TL/H/11354– 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

COPS

microcontrollers, HPC

and MICROWIRE

are trademarks of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Summary of content (42 pages)

PAGE 1
ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description Features The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. The ADC12032/ ADC12H032, ADC12034/ADC12H034 and ADC12038/ ADC12H038 have 2, 4 and 8 channel multiplexers, respectively.
PAGE 2
Connection Diagrams 20-Pin Dual-In-Line and Wide Body SO Packages 16-Pin Dual-In-Line and Wide Body SO Packages TL/H/11354–6 Top View Top View 28-Pin Dual-In-Line and Wide Body SO Packages 24-Pin Dual-In-Line and Wide Body SO Packages Top View TL/H/11354 – 7 TL/H/11354–8 Top View Ordering Information Industrial Temperature Range b 40§ C s TA s a 85§ C Package ADC12H030CIN, ADC12030CIN N16E ADC12H030CIWM, ADC12030CIWM M16B ADC12H032CIN, ADC12032CIN N20A ADC12H032CIWM, ADC12032CIWM M20B A
PAGE 3
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) Operating Temperature Range TMIN s TA s TMAX ADC12030CIN, ADC12030CIWM, ADC12H030CIN, ADC12H030CIWM, ADC12032CIN, ADC12032CIWM, ADC12H032CIN, ADC12H032CIWM, ADC12034CIN, ADC12034CIWM, ADC12H034CIN, ADC12H034CIWM, ADC12038CIN, ADC12038CIWM, ADC12H038CIN, b 40§ C s TA s a 85§ C ADC12H038CIWM a 4.5V to a 5.
PAGE 4
Converter Electrical Characteristics (Continued) The following specifications apply for V a e VA a e VD a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK e fSK e 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
PAGE 5
Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK e fSK e 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
PAGE 6
DC and Logic Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK e fSK e 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
PAGE 7
AC Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, tr e tf e 3 ns, fCK e fSK e 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK e fSK e 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
PAGE 8
AC Electrical Characteristics (Continued) The following specifications apply for V a e VA a e VD a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, tr e tf e 3 ns, fCK e fSK e 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK e fSK e 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 2.
PAGE 9
Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
PAGE 10
Electrical Characteristics (Continued) TL/H/11354 – 10 FIGURE 1a. Transfer Characteristic TL/H/11354 – 11 FIGURE 1b.
PAGE 11
Electrical Characteristics (Continued) TL/H/11354 – 12 FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle TL/H/11354 – 13 FIGURE 2.
PAGE 12
Typical Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified. The performance for 8-bit a sign mode is equal to or better than shown.
PAGE 13
Typical Performance Characteristics (Continued) The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified. The performance for 8-bit a sign mode is equal to or better than shown. Analog Supply Current vs Temperature Digital Supply Current vs Clock Frequency Digital Supply Current vs Temperature TL/H/11354 – 15 Typical Dynamic Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
PAGE 14
Typical Dynamic Performance Characteristics (Continued) The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
PAGE 15
Test Circuits DO ‘‘TRI-STATE’’ (t1H, t0H) DO except ‘‘TRI-STATE’’ TL/H/11354 – 3 TL/H/11354 – 4 Leakage Current TL/H/11354 – 5 Timing Diagrams DO Falling and Rising Edge DO ‘‘TRI-STATE’’ Falling and Rising Edge TL/H/11354 – 18 TL/H/11354 – 19 DI Data Input Timing TL/H/11354 – 20 15
PAGE 16
Timing Diagrams (Continued) DO Data Output Timing Using CS TL/H/11354 – 21 DO Data Output Timing with CS Continuously Low TL/H/11354 – 22 ADC12038 Auto Cal or Auto Zero TL/H/11354 – 23 Note: DO output data is not valid during this cycle.
PAGE 17
Timing Diagrams (Continued) ADC12038 Read Data without Starting a Conversion Using CS TL/H/11354 – 24 ADC12038 Read Data without Starting a Conversion with CS Continuously Low TL/H/11354 – 25 17
PAGE 18
Timing Diagrams (Continued) ADC12038 Conversion Using CS with 8-Bit Digital Output Format TL/H/11354 – 26 ADC12038 Conversion Using CS with 16-Bit Digital Output Format TL/H/11354 – 51 18
PAGE 19
Timing Diagrams (Continued) ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format TL/H/11354 – 28 ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format TL/H/11354 – 29 19
PAGE 20
Timing Diagrams (Continued) ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format TL/H/11354 – 52 ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format TL/H/11354 – 31 20
PAGE 21
Timing Diagrams (Continued) ADC12038 Hardware Power Up/Down TL/H/11354 – 32 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register.
PAGE 22
Pin Descriptions CCLK SCLK DI DO EOC CS turely terminated. The data in the output latches may be corrupted. Therefore, when CS is brought back low during a conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied it expects to see 13 clock pulses for each I/O sequence.
PAGE 23
Pin Descriptions (Continued) VREF a This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF e VREF a b VREFb) is 1 VDC to 5.0 VDC and the voltage at VREF a cannot exceed VA a . See Figure 4 for recommended bypassing. VREFb The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND or exceed VA a . (See Figure 4 ). VA a , VD a These are the analog and digital power supply pins.
PAGE 24
Tables TABLE I.
PAGE 25
Tables (Continued) TABLE III.
PAGE 26
Tables (Continued) TABLE V.
PAGE 27
Tables (Continued) TABLE VII. Status Register Status Bit Location DB0 Status Bit PU DB1 DB2 DB3 DB4 PD Cal 8 or 9 12 or 13 Device Status ‘‘High’’ indicates a Power Up Function Sequence is in progress ‘‘High’’ indicates a Power Down Sequence is in progress DB5 DB6 DB7 DB8 16 or 17 Sign Justification Test Mode When ‘‘High’’ the conversion result will be output MSB first. When ‘‘Low’’ the result will be output LSB first. When ‘‘High’’ the device is in test mode.
PAGE 28
Application Hints (Continued) In Figure 6 the only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in Figure 6 , to set CH1 as the positive input and CH0 as the negative input for the different versions of ADCs: it will expect to see 13 SCLK pulses for each I/O transmission.
PAGE 29
Application Hints (Continued) After returning to user mode with the user mode instruction the power up, data with or without sign, and acquisition time instructions need to be resent to ensure that the ADC is in the required state before a conversion is started. 1.6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CH0 – CH7 become active outputs.
PAGE 30
Application Hints (Continued) The Multiplexer assignment tables for the ADC12030,2,4,8 (Tables II, III, and IV) summarize the aforementioned functions for the different versions of A/Ds. With the single-ended multiplexer configuration CH0 through CH7 can be assigned to the MUXOUT1 pin. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positve input; A/DIN2 is assigned as the negative input. (See Figure 8 ). Differential Configuration 2.
PAGE 31
Application Hints (Continued) periods, the input biasing resistor needs to be 600X or less. Notice though that the input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600X to increase to 6k, which with a 1 mF coupling capacitor would set the high pass corner at 26 Hz. Increasing R, to 6k would allow R2 to be 2k.
PAGE 32
Application Hints (Continued) TL/H/11354 – 49 FIGURE 12. Pseudo-Differential Biasing without the Loss of Digital Output Range TL/H/11354 – 50 FIGURE 13.
PAGE 33
Application Hints (Continued) 3.0 REFERENCE VOLTAGE The difference in the voltages applied to the VREF a and VREFb defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage sources driving VREF a or VREFb must have very low output impedance and noise.
PAGE 34
Application Hints (Continued) 8.0 NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the noise sources. 6.
PAGE 35
Application Hints (Continued) noise a distortion ratio (S/(N a D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability. An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform.
PAGE 36
Application Hints (Continued) TL/H/11354 – 44 Note: VA a , VD a , and VREF a on the ADC12038 each have 0.01 mF and 0.1 mF chip caps, and 10 mF tantalum caps. All logic devices are bypassed with 0.1 mF caps.
PAGE 37
Application Hints (Continued) ’variables DOL4Data Out word length, DI4Data string for A/D DI input, ’ DO4A/D result string ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS HIGH OUT &H3FC, (&HFE AND INP(&H3FC)) ’set DTR LOW OUT &H3FC, (&HFD AND INP(&H3FC)) ’set RTS LOW OUT &H3FC, (&HEF AND INP(&H3FC)) ’set B4 low 10 LINE INPUT ‘DI data for ADC12038 (see Mode Table on data sheet)‘; DI$ INPUT ‘ADC12038 output word length (8,9,12,13,16 or 17)‘; DOL 20 ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS
PAGE 38
Physical Dimensions inches (millimeters) Order Number ADC12030CIWM or ADC12H030CIWM NS Package Number M16B Order Number ADC12032CIWM or ADC12H032CIWM NS Package Number M20B 38
PAGE 39
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12034CIWM or ADC12H034CIWM NS Package Number M24B Order Number ADC12038CIWM or ADC12H038CIWM NS Package Number M28B 39
PAGE 40
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12030CIN or ADC12H030CIN NS Package Number N16E Order Number ADC12032CIN or ADC12H032CIN NS Package Number N20A 40
PAGE 41
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12034CIN or ADC12H034CIN NS Package Number N24C 41
PAGE 42
ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold Physical Dimensions inches (millimeters) (Continued) Order Number ADC12038CIN or ADC12H038CIN NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION.