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TL/H/12387

ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter

December 1995

ADC12048

12-Bit Plus Sign 216 kHz 8-Channel Sampling

Analog-to-Digital Converter

General Description

Operating from a single 5V power supply the ADC12048 is a

12 bit

sign, parallel I/O, self-calibrating, sampling analog-

to-digital converter (ADC) with an eight input fully differential

analog multiplexer. The maximum sampling rate is 216 kHz.

On request, the ADC goes through a self-calibration pro-

cess that adjusts linearity, zero and full-scale errors.

The ADC12048’s 8-channel multiplexer is software pro-

grammable to operate in a variety of combinations of single-

ended, differential, or pseudo-differential modes. The fully

differential MUX and the 12-bit

sign ADC allows for the

difference between two signals to be digitized.

The ADC12048 can be configured to work with many popu-

lar microprocessors/microcontrollers including National’s

HPC family, Intel386 and 8051, TMS320C25, Motorola

MC68HC11/16, Hitachi 64180 and Analog Devices

ADSP21xx.

For complementary voltage references see the LM4040,

LM4041 or LM9140.

Key Specifications (f

CLK

12 MHz)

Resolution 12-bits

sign

13-bit conversion time 3.6 ms, max

13-bit throughput rate 216 ksamples/s, min

Integral Linearity Error (ILE)

1 LSB, max

Single Supply

10%

Range GND to V

Power consumption:

Normal operation 34 mW, max

Stand-by mode 75 mw, max

Features

8-channel programmable Differential or Single-Ended

multiplexer

Programmable Acquisition Times and user-controllable

Throughput Rates

Programmable data bus width (8/13 bits)

Built-in Sample-and-Hold

Programmable Auto-Calibration and Auto-Zero cycles

Low power standby mode

No missing codes

Applications

Medical instrumentation

Process control systems

Test equipment

Data logging

Inertial guidance

Block Diagram

TL/H/12387–1

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.

Summary of content (30 pages)

PAGE 1
ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter Y General Description Y Operating from a single 5V power supply the ADC12048 is a 12 bit a sign, parallel I/O, self-calibrating, sampling analogto-digital converter (ADC) with an eight input fully differential analog multiplexer. The maximum sampling rate is 216 kHz. On request, the ADC goes through a self-calibration process that adjusts linearity, zero and full-scale errors.
PAGE 2
Connection Diagrams PQFP Package PLCC Package TL/H/12387–2 TL/H/12387 – 3 Order Number ADC12048CIV See NS Package Number V44A Order Number ADC12048CIVF See NS Package Number VGZ44A Ordering Information Industrial Temperature Range b 40§ C s TA s a 85§ C ADC12048CIV ADC12048CIVF 2 Package V44A VGZ44A
PAGE 3
Absolute Maximum Ratings (Notes 1 and 2) Lead Temperature VF Package Vapor Phase (60 sec.) Infared (15 sec.) V Package, Infared (15 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VA a and VD a ) Voltage at all Inputs lVA a b VD a l lAGND b DGNDl Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) at TA e 25§ C Storage Temperature 6.
PAGE 4
Power Supply Characteristics The following specifications apply to the ADC12048 for VA a e VD a e 5V, VREF a e 4.096V, VREFb e 0.0V, 12-bit a sign conversion mode, fCLK e 12.0 MHz, RS e 25X, source impedance for VREF a and VREFb s 1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
PAGE 5
Reference Inputs The following specifications apply to the ADC12048 for VA a e VD a e 5V, VREF a e 4.096V, VREFb e 0.0V, 12-bit a sign conversion mode, fCLK e 12.0 MHz, RS e 25X, source impedance for VREF a and VREFb s 1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
PAGE 6
Digital Timing Characteristics The following specifications apply to the ADC12048, 13-bit data bus width, VA a e VD a e 5V, fCLK e 12 MHz, tf e 3 ns and CL e 50 pF on data I/O lines Symbol (Figure 7) tTPR Parameter Throughput Rate Conditions Sync-Out Mode (SYNC Bit e ‘‘0’’) 9 Clock Cycles of Acquisition Time Typical (Note 10) Limits (Note 11) Units (Limit) 222 kHz tCSWR Falling Edge of CS to Falling Edge of WR 0 tWRCS Active Edge of WR to Rising Edge of CS 0 ns tWR WR Pulse Width 20 tWRSETF
PAGE 7
Notes on Specifications (Continued) Note 6: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above VA a or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion can occur if these diodes are forward biased by more than 50 mV. As an example, if VA a is 4.50 VDC, full-scale input voltage must be s 4.
PAGE 8
Electrical Characteristics TL/H/12387 – 5 FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case) TL/H/12387 – 6 FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for VREF e 4.
PAGE 9
Electrical Characteristics (Continued) TL/H/12387 – 7 FIGURE 3. VREF Operating Range (General Case) TL/H/12387 – 8 FIGURE 4.
PAGE 10
Electrical Characteristics (Continued) TL/H/12387 – 9 FIGURE 5a. Transfer Characteristic TL/H/12387 – 10 FIGURE 5b.
PAGE 11
Electrical Characteristics (Continued) TL/H/12387 – 11 FIGURE 5c. Simplified Error vs Output Code after Auto-Calibration Cycle TL/H/12387 – 12 FIGURE 6.
PAGE 12
Timing Diagrams TL/H/12387 – 13 FIGURE 7a. Sync-Out Write (WMODE e 1, BW e 1), Read and Convert Cycles TL/H/12387 – 14 FIGURE 7b.
PAGE 13
Timing Diagrams (Continued) TL/H/12387 – 46 FIGURE 7c. Sync-Out Write (WMODE e 0, BW e 1), Read and Convert Cycles TL/H/12387 – 47 FIGURE 7d.
PAGE 14
Timing Diagrams (Continued) TL/H/12387 – 48 FIGURE 7e. Sync-Out Read and Convert Cycles. The MUX channel is the channel selected on the most recent write cycle. TL/H/12387 – 49 FIGURE 7f. Sync-In Read and Convert Cycles. The MUX channel is the channel selected on the most recent write cycle.
PAGE 15
Timing Diagrams (Continued) TL/H/12387 – 50 FIGURE 7g. 8-Bit Bus Read Cycle (Sync-Out) TL/H/12387 – 51 FIGURE 7h.
PAGE 16
Timing Diagrams (Continued) TL/H/12387 – 15 FIGURE 7i. Write Signal Negates RDY (Writing the Standby, Auto-Cal or Auto-Zero Command) TL/H/12387 – 16 FIGURE 7j.
PAGE 17
Typical Performance Characteristics Integral Linearity Error (INL) Change vs Clock Frequency (See Note 19, Electrical Characteristic Section) Full-Scale Error Change vs Clock Frequency TL/H/12387 – 18 TL/H/12387–17 Integral Linearity Error (INL) Change vs Temperature Full-Scale Error Change vs Temperature TL/H/12387–20 Integral Linearity Error (INL) Change vs Reference Voltage TL/H/12387 – 21 Full-Scale Error Change vs Reference Voltage TL/H/12387 – 24 TL/H/12387–23 Integral Linearity Error (IN
PAGE 18
Typical Performance Characteristics (Continued) (See Note 21, Electrical Characteristic Section) Reference Currents vs Clock Frequency Supply Currents vs Clock Frequency TL/H/12387–42 TL/H/12387 – 43 Analog Supply Current vs Temperature Digital Supply Current vs Temperature TL/H/12387–44 TL/H/12387 – 45 18
PAGE 19
Typical Performance Characteristics (Continued) The curves were obtained under the following conditions. RS e 50X, TA e 25§ C, VA a e VD a e 5V, VREF e 4.096V, fCLK e 12 MHz, and the sampling rate fS e 215 kHz unless otherwise stated.
PAGE 20
Pin Description PLCC Pkg. Pin Number PQFP Pkg. Pin Number 6 7 8 9 15 16 17 18 44 1 2 3 9 10 11 12 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 The eight analog inputs to the Multiplexer. Active channels are selected based on the contents of bits b3–b0 of the Configuration register. Refer to section titled MUX for more details. 14 8 COM This pin is another analog input pin used as a pseudo ground when the multiplexer is configured in single-ended mode. 13 7 VREF a Positive reference input.
PAGE 21
Register Bit Description CONFIGURATION REGISTER (Write Only) This is a 13-bit write-only register that is used to program the functionality of the ADC12048. All data written to the ADC12048 will always go to this register only. The contents of this register cannot be read. MSB LSB b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 COMMAND BW SYNC HB SE ACQ TIME MUX ADDRESS FIELD Power on State: 0100Hex b3 –b0: The MUX ADDRESS bits configure the analog input MUX.
PAGE 22
can be used at the output of the multiplexer before being applied to the ADC inputs. The ADCIN a and ADCINb are the fully differential non-inverting (positive) and inverting (negative) inputs to the analog-to-digital converter (ADC) of the ADC12048. If no external signal conditioning is required on the signal output of the multiplexer, MUXOUT a should be connected to ADCIN a and MUXOUTb should be connected to ADCINb.
PAGE 23
Features and Operating Modes (Continued) Once the converter has been calibrated, an arithmetic logic unit (ALU) uses the offset and linearity correction coefficients to reduce the conversion offset and linearity errors to within guaranteed limits. less than 1 kX and any active or reactive source circuitry settles to 12 bits in less than 500 ns. When source resistance or source settling time increase beyond these limits, the acquisition time must also be increased to preserve precision.
PAGE 24
Features and Operating Modes (Continued) The RDY signal will go low when the conversion is done. A new MUX channel and/or operational command may be written into the Configuration register at this time, if needed. Two consecutive read cycles are required to retrieve the entire 13-bit conversion result from the ADC12048’s data register. The first read will place the lower byte of the conversion result contained in the Data register on the data bus.
PAGE 25
Analog Application Information input voltage is proportional to the voltage used for the ADC’s reference voltage. This technique relaxes the system reference requirements because the analog input voltage moves with the ADC’s reference. The system power supply can be used as the reference voltage by connecting the VREF a pin to VA a and the VREFb pin to AGND.
PAGE 26
Analog Application Information (Continued) on the PC board. All supply currents should be supplied by the capacitor instead of being drawn from the external supply lines, while the external supply charges the capacitor at a steady rate. The ADC has two VD a and DGND pins. It is recommended to use a 0.1 mF plus a 10 mF capacitor between pins 15 and 16 (VD a ) and 14 (DGND) and a 0.1 mF capacitor between pins 28 (VD a ) and 1 (DGND) for the PLCC package.
PAGE 27
Analog Application Information (Continued) TL/H/12387 – 38 FIGURE 10. Top View of Printed Circuit Board for a 44-Pin PLCC ADC12048 Figure 10 also shows the reference input bypass capacitors. Here the reference inputs are considered to be differential. The performance improves by having a 0.1 mF capacitor between the VREF a and VREFb, and by bypassing in a manner similar to that described for the supply pins.
PAGE 28
PAGE 29
Physical Dimensions inches (millimeters) 44-Lead Molded Plastic Leaded Chip Carrier Order Number ADC12048CIV NS Package Number V44A 29
PAGE 30
ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter Physical Dimensions inches (millimeters) (Continued) 44-Lead (10mm x 10mm) Molded Plastic Quad Flat Package Order Number ADC12048CIVF NS Package Number VGZ44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.