ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description Features The ADC12130, ADC12132 and ADC12138 are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexer. The ADC12132 and ADC12138 have a 2 and an 8 channel multiplexer, respectively. The differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins.
Connection Diagrams 28-Pin Dual-In-Line, SSOP and Wide Body SO Packages 16-Pin Dual-In-Line and Wide Body SO Packages TL/H/12079–2 Top View 20-Pin SSOP Package TL/H/12079 – 3 Top View TL/H/12079–47 Top View Ordering Information Industrial Temperature Range b 40§ C s TA s a 85§ C ADC12130CIN NS Package Number N16E, Dual-In-Line ADC12130CIWM M16B, Wide Body SO ADC12132CIMSA MSA20, SSOP ADC12138CIN N28B, Dual-In-Line ADC12138CIWM M28B ADC12138CIMSA MSA28, SSOP 2
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Temperature Range TMIN s TA s TMAX ADC12130CIN, ADC12130CIWM, ADC12132CIMSA, ADC12138CIMSA, ADC12138CIN, ADC12138CIWM b40§ C s TA s a 85§ C a 3.0V to a 5.
Converter Electrical Characteristics The following specifications apply for (V a e VA a e VD a e a 5V, VREF a e a 4.096V, and fully differential input with fixed 2.048V common-mode voltage) or (V a e VA a e VD a e 3.3V, VREF a e a 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREFb e 0V, 12-bit a sign conversion mode, source impedance for analog inputs, VREFb and VREF a s 25X, fCK e fSK e 5 MHz, and 10 (tCK) acquisition time unless otherwise specified.
Electrical Characteristics The following specifications apply for (V a e VA a e VD a e a 5V, VREF a e a 4.096V, and fully differential input with fixed 2.048V common-mode voltage) or (V a e VA a e VD a e a 3.3V, VREF a e 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREFb e 0V, 12-bit a sign conversion mode, source impedance for analog inputs, VREFb and VREF a s 25X, fCK e fSK e 5 MHz, and 10 (tCK) acquisition time unless otherwise specified.
DC and Logic Electrical Characteristics The following specifications apply for (V a e VA a e VD a e a 5V, VREF a e a 4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V a e VA a e VD a e a 3.3V, VREF a e a 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREFb e 0V, 12-bit a sign conversion mode, source impedance for analog inputs, VREFb and VREF a s 25X, fCK e fSK e 5 MHz, and 10 (tCK) acquisition time unless otherwise specified.
AC Electrical Characteristics The following specifications apply for (V a e VA a e VD a e a 5V, VREF a e a 4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V a e VA a e VD a e a 3.3V, VREF a e a 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREFb e 0V, 12-bit a sign conversion mode, source impedance for analog inputs, VREFb and VREF a s 25X, fCK e fSK e 5 MHz, and 10 (tCK) acquisition time unless otherwise specified.
AC Electrical Characteristics The following specifications apply for (V a e VA a e VD a e a 5V, VREF a e a 4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V a e VA a e VD a e a 3.3V, VREF a e a 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREFb e 0V, 12-bit a sign conversion mode, source impedance for analog inputs, VREFb and VREF a s 25X, fCK e fSK e 5 MHz, and 10 (tCK) acquisition time unless otherwise specified.
AC Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
AC Electrical Characteristics (Continued) TL/H/12079 – 5 FIGURE 1a. Transfer Characteristic TL/H/12079 – 6 FIGURE 1b.
AC Electrical Characteristics (Continued) TL/H/12079 – 7 FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle TL/H/12079 – 8 FIGURE 2.
Typical Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
Typical Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
Typical Dynamic Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
Typical Dynamic Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified.
Test Circuits DO ‘‘TRI-STATE’’ (t1H, t0H) DO except ‘‘TRI-STATE’’ TL/H/12079–13 TL/H/12079 – 14 Leakage Current TL/H/12079 – 15 Timing Diagrams DO Falling and Rising Edge DO ‘‘TRI-STATE’’ Falling and Rising Edge TL/H/12079–16 TL/H/12079 – 17 DI Data Input Timing TL/H/12079 – 18 16
Timing Diagrams (Continued) DO Data Output Timing Using CS TL/H/12079 – 19 DO Data Output Timing with CS Continuously Low TL/H/12079 – 20 ADC12138 Auto Cal or Auto Zero TL/H/12079 – 21 Note: DO output data is not valid during this cycle.
Timing Diagrams (Continued) ADC12138 Read Data without Starting a Conversion Using CS TL/H/12079 – 22 ADC12138 Read Data without Starting a Conversion with CS Continuously Low TL/H/12079 – 23 18
Timing Diagrams (Continued) ADC12138 Conversion Using CS with 16-Bit Digital Output Format TL/H/12079 – 24 ADC12138 Conversion with CS Continuously Low and 16-Bit Digital Output Format TL/H/12079 – 25 19
Timing Diagrams (Continued) ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format TL/H/12079 – 26 ADC12138 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format TL/H/12079 – 27 20
Timing Diagrams (Continued) ADC12138 Hardware Power Up/Down TL/H/12079 – 28 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register.
Pin Descriptions CCLK SCLK DI DO EOC CS time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin.
Pin Descriptions (Continued) VREFb VA a , VD a DGND AGND The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND or exceed VA a . (See Figure 4 ). These are the analog and digital power supply pins. VA a and VD a are not connected together on the chip. These pins should be tied to the same power supply and bypassed separately (see Figure 4 ). The operating voltage range of VA a and VD a is 3.0 VDC to 5.5 VDC.
Tables TABLE I.
Tables (Continued) TABLE III. ADC12130 and ADC12132 Multiplexer Addressing Analog Channel Addressed and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 MUX Address DI0 DI1 CH0 CH1 L L L H a b b a H H L H a COM Mode A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 a b b a CH0 CH0 CH1 CH1 Differential a a b b CH0 CH1 COM COM Single-Ended b b a Multiplexer Output Channel Assignment A/D Input Polarity Assignment Note: ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.
Tables (Continued) TABLE VI. Status Register Status Bit Location DB0 Status Bit PU DB1 DB2 PD Cal DB3 DB4 12 or 13 Device Status ‘‘High’’ indicates a Power Up Function Sequence is in progress ‘‘High’’ indicates a Power Down Sequence is in progress DB5 DB6 DB7 DB8 16 or 17 Sign Justification Test Mode When ‘‘High’’ the conversion result will be output MSB first. When ‘‘Low’’ the result will be output LSB first. When ‘‘High’’ the device is in test mode.
Application Hints (Continued) In Figure 6 the only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in Figure 6 , to set CH1 as the positive input and CH0 as the negative input for the different versions of ADCs: it will expect to see 13 SCLK pulses for each I/O transmission.
Application Hints (Continued) After returning to user mode with the user mode instruction the power up, data with or without sign, and acquisition time instructions need to be resent to ensure that the ADC is in the required state before a conversion is started. 1.6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CH0– CH7 become active outputs.
Application Hints (Continued) The Multiplexer assignment tables for the ADC12130/2/8 (Tables II and III) summarize the aforementioned functions for the different versions of A/Ds. With the single-ended multiplexer configuration CH0 through CH7 can be assigned to the MUXOUT1 pin. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positve input; A/DIN2 is assigned as the negative input. (See Figure 8 ). Differential Configuration 2.
Application Hints (Continued) to an acquisition time of 10 clock periods, the input biasing resistor needs to be 600X or less. Notice though that the input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600X to increase to 6k, which with a 1 mF coupling capacitor would set the high pass corner at 26 Hz. Increasing R, to 6k would allow R2 to be 2k.
Application Hints (Continued) TL/H/12079 – 41 FIGURE 12. Pseudo-Differential Biasing without the Loss of Digital Output Range TL/H/12079 – 42 FIGURE 13.
Application Hints (Continued) 3.0 REFERENCE VOLTAGE The difference in the voltages applied to the VREF a and VREFb defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage sources driving VREF a or VREFb must have very low output impedance and noise.
Application Hints (Continued) 6.0 INPUT SOURCE RESISTANCE 8.0 NOISE For low impedance voltage sources (k600X), the input charging current will decay, before the end of the S/H’s acquisition time of 2 ms (10 CCLK periods with fCK e 5 MHz), to a value that will not introduce any conversion errors. For high source impedances, the S/H’s acquisition time can be increased to 18 or 34 CCLK periods. For less ADC accuracy and/or slower CCLK frequencies the S/H’s acquisition time may be decreased to 6 CCLK periods.
Application Hints (Continued) er bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability. An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N a D) and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained.
Application Hints (Continued) TL/H/12079 – 46 Note: VA a , VD a , and VREF a on the ADC12138 each have 0.01 mF and 0.1 mF chip caps, and 10 mF tantalum caps. All logic devices are bypassed with 0.1 mF caps. The assignment of the RS232 port is shown below COM1 B7 B6 B5 B4 B3 B2 B1 Input Address 3FE X X X CTS X X X B0 X Output Address 3FC X X X 0 X X RTS DTR Acquisition Time, 12-bit conversion, data out with sign, power up, 12- or 13-bit MSB First, and user mode.
Application Hints (Continued) ’variables DOL4Data Out word length, DI4Data string for A/D DI input, ’ DO4A/D result string ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC) OUT &H3FC, (&HFE AND INP(&H3FC) OUT &H3FC, (&HFD AND INP (&H3FC) ’set RTS HIGH ’SET DTR LOW ’SET RTS LOW OUT &H3FC, (&HEF AND INP(&H3FC)) ’set B4 low 10 LINE INPUT ‘DI data for ADC12138 (see Mode Table on data sheet)‘; DI$ INPUT ‘ADC12138 output word length (12,13,16 or 17)‘; DOL 20 ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC) OUT &H3FC, (&
Physical Dimensions inches (millimeters) Order Number ADC12130CIWM NS Package Number M16B Order Number ADC12138CIWM NS Package Number M28B 37
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12132CIMSA NS Package Number MSA20 Order Number ADC12138CIMSA NS Package Number MSA28 38
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12130CIN NS Package Number N16E 39
ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold Physical Dimensions inches (millimeters) (Continued) Order Number ADC12138CIN NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
