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ADC12181

12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter

with Internal Sample & Hold

General Description

The ADC12181 is a monolithic CMOS analog-to-digital con-

verter capable of converting analog input signals into 12-bit

digital words at 10 megasamples per second (MSPS). The

ADC12181 utilizes an innovative pipeline architecture to

minimize die size and power consumption. Self-calibration

and error correction maintain accuracy and performance

over temperature.

The ADC12181 converter operates on a 5V power supply

and can digitize analog input signals in the range of 0 to 2V.

A single convert clock controls the conversion operation. All

digital I/O is TTL compatible.

The ADC12181 is designed to minimize external compo-

nents necessary for the analog input interface. An internal

sample-and-hold circuit samples the analog input and an

internal amplifier buffers the reference voltage input.

The ADC12181 is available in the 32-lead TQFP package

and is designed to operate over the extended commercial

temperature range of -40˚C to +85˚C.

Features

n Single 5V power supply

n Simple analog input interface

n Internal Sample-and-hold

n Internal Reference buffer amplifier

n Low power consumption

Key Specifications

n Resolution 12 Bits

n Conversion Rate 10 Msps (min)

n DNL

0.4 LSB (typ)

n SNR 65 dB (typ)

n ENOB 10.4 Bits (typ)

n Analog Input Range 2 Vpp (min)

n Supply Voltage +5V

n Power Consumption, 10 MHz 235 mW (typ)

Applications

n Image processing front end

n PC-based data acquisition

n Scanners

n Fax machines

n Waveform digitizer

Connection Diagram

10103901

Ordering Information

Industrial

(−40˚C ≤ TA ≤ +85˚C) Package

ADC12181CIVT 32 pin TQFP

November 2002

ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold

Summary of content (17 pages)

PAGE 1
ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold General Description The ADC12181 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 10 megasamples per second (MSPS). The ADC12181 utilizes an innovative pipeline architecture to minimize die size and power consumption. Self-calibration and error correction maintain accuracy and performance over temperature.
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ADC12181 Ordering Information (Continued) Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12181 EVAL Evaluation Board Simplified Block Diagram 10103902 www.national.
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No. Symbol Equivalent Circuit Description VIN Analog signal input. With a 2.0V reference voltage, input signal voltages in the range of 0 to 2.0 Volts will be converted. See section 1.2. 1 VREF Reference voltage input. This pin should be driven from an accurate, stable reference source in the range of 1.8 to 2.2V and bypassed to a low-noise analog ground with a monolithic ceramic capacitor, nominally 0.01µF. See section 1.1. 32 VRP Positive reference bypass pin. Bypass with a 0.1µF capacitor.
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ADC12181 Pin Descriptions and Equivalent Circuits #2 No. Symbol 14-19, 22-27 D0 - D11 3 VIN com Equivalent Circuit (Continued) Description Digital output word, CMOS compatible. D0 (pin 14) is LSB, D11 (pin 27) is MSB. Load with no more than 50pF. Analog input common. Connect to a quiet point in analog ground near the driving device. See section 1.2. 5 VA Positive analog supply pin. Connect to a clean, quiet voltage source of +5V.
PAGE 5
Storage Temp. (Notes 1, −65˚C to +150˚C 2) Maximum Junction Temp. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Ratings Supply Voltage Supply Voltage −0.3V to V+ +0.3V Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation ± 25mA ± 50mA VD I/O +2.7V to VD VREF Input 1.8V to 2.2V −0.05V to VD + 0.
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ADC12181 DC and Logic Electrical Characteristics The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V, fCLK = 10MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = TJ = 25˚C (Note 7) (Note 8) and (Note 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) CLK, OE Digital Input Characteristics VIH Logical "1" Input Voltage V+ = 5.25V 2.
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(Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
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ADC12181 Transfer Characteristics 10103909 FIGURE 1. Transfer Characteristic 10103910 FIGURE 2. Errors Minimized by the Auto-Cal Cycle Typical Performance Characteristics INL vs Temperature DNL vs Temperature 10103911 www.national.
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ADC12181 Typical Performance Characteristics (Continued) SNR vs Temperature SINAD vs Temperature 10103913 10103914 THD vs Temperature 10103915 10103916 10103917 9 www.national.
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ADC12181 PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and the availability of that conversion result at the output. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay plus the Output Delay. SAMPLING (APERTURE) DELAY is the time after the edge of the clock to when the input signal is acquired or held for conversion.
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ADC12181 Timing Diagrams 10103921 FIGURE 3. Data Output Timing 11 www.national.
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ADC12181 Timing Diagrams (Continued) 10103922 FIGURE 4. Reset and Calibration Timing Functional Description Applications Information The ADC12181 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 10 megasamples per second (MSPS). This device utilizes a proprietary pipeline architecture and algorithm to minimize die size and power consumption.
PAGE 13
3.3 OR (Out of Range) Output (Continued) The OR output goes high when the analog input is below GND or above VREF. This output is low when the input signal is in the valid range of operation (0V ≤ VIN ≤ VREF). 2.2 CAL The level sensitive CAL input must be pulsed high for at least three clock cycles to begin ADC calibration.
PAGE 14
ADC12181 Applications Information (Continued) 10103923 FIGURE 5. Basic Connections Diagram 5.0 LAYOUT AND GROUNDING Proper grounding and routing of all signals is essential to ensure accurate conversion. Separate analog and digital ground planes that are connected beneath the ADC12181 are required to achieve specified performance. The analog and digital grounds may be in the same layer, but should be separated from each other and should never overlap each other.
PAGE 15
which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. (Continued) should be avoided as even a little coupling can cause problems at high frequencies. This is because other lines can introduce phase noise (jitter) into the clock line, which can lead to degradation of SNR. Best performance at high frequencies and at high resolution is obtained with a straight signal path.
PAGE 16
ADC12181 Applications Information separate analog and digital ground planes will reduce this problem. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12181, reducing the energy coupled back into the converter output pins by limiting the output slew rate. A reasonable value for these resistors is 47Ω. Using an inadequate amplifier to drive the analog input.
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inches (millimeters) 32-Lead TQFP Package Ordering Number ADC12181CIVT NS Package Number VBE32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.