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TL/H/10554

ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold

November 1994

ADC1241 Self-Calibrating 12-Bit Plus

Sign mP-Compatible A/D Converter

with Sample-and-Hold

General Description

The ADC1241 is a CMOS 12-bit plus sign successive ap-

proximation analog-to-digital converter. On request, the

ADC1241 goes through a self-calibration cycle that adjusts

positive linearity and full-scale errors to less than

(/2 LSB

each and zero error to less than

1 LSB. The ADC1241

also has the ability to go through an Auto-Zero cycle that

corrects the zero error during every conversion.

The analog input to the ADC1241 is tracked and held by the

internal circuitry, and therefore does not require an external

sample-and-hold. A unipolar analog input voltage range (0V

5V) or a bipolar range (

5V to

5V) can be accom-

modated with

5V supplies.

The 13-bit word on the outputs of the ADC1241 gives a 2’s

complement representation of negative numbers. The digi-

tal inputs and outputs are compatible with TTL or CMOS

logic levels.

Applications

Digital Signal Processing

High Resolution Process Control

Instrumentation

Key Specifications

Resolution 12 Bits plus Sign

Conversion Time 13.8ms (max)

Linearity Error

(/2 LSB (

0.0122%) (max)

Zero Error

1LSB (max)

Positive Full Scale Error

1LSB (max)

Power Consumption 70mW (max)

Features

Self-calibrating

Internal sample-and-hold

Bipolar input range with

5V supplies and single

5V reference

No missing codes over temperature

TTL/MOS input/output compatible

Standard 28-pin DIP

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

Simplified Schematic

TL/H/10554–1

Connection Diagram

Dual-In-Line Package

TL/H/10554–2

Top View

Order Number ADC1241CMJ,

ADC1241CMJ/883, ADC1241BIJ or

ADC1241CIJ

See NS Package Number J28A

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (14 pages)

PAGE 1
ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold General Description Key Specifications The ADC1241 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the ADC1241 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than g (/2 LSB each and zero error to less than g 1 LSB.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) Temperature Range TMINsTAsTMAX b 40§ C s TA s a 85§ C ADC1241BIJ, ADC1241CIJ ADC1241CMJ, ADC1241CMJ/883 b55§ CsTAs a 125§ C DVCC and AVCC Voltage (Notes 6 & 7) 4.5V to 5.5V b 4.5V to b 5.5V Negative Supply Voltage (Vb) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC e DVCC e AVCC) 6.5V b 6.
PAGE 3
Digital and DC Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, and fCLK e 2.0 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) Symbol Parameter Condition Typical (Note 9) Limit (Notes 10, 18) Units (Limits) VIN(1) Logical ‘‘1’’ Input Voltage for All Inputs except CLK IN VCC e 5.25V 2.
PAGE 4
AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, tr e tf e 20 ns unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) Symbol fCLK Parameter Conditions Typical (Note 9) Limit (Notes 10, 18) Units (Limits) 2.0 MHz MHz(min) MHZ(max) Clock Frequency 0.5 4.0 Clock Duty Cycle tC 50 Conversion Time Acquisition Time (Note 15) tZ Auto Zero Time RSOURCE e 50X fCLK e 2.
PAGE 5
AC Electrical Characteristics (Continued) Note 7: A diode exists between AVCC and DVCC as shown below. TL/H/10554 – 4 To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin. Note 8: Accuracy is guaranteed at fCLK e 2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance Characteristics Section.
PAGE 6
AC Electrical Characteristics (Continued) TL/H/10554 – 6 FIGURE 1b. Simplified Error Curve vs Output Code Without Auto-Cal or Auto-Zero Cycles TL/H/10554 – 7 FIGURE 1c.
PAGE 7
Typical Performance Characteristics (Continued) Linearity Error vs VREF Linearity Error vs Clock Frequency Full Scale Error Change vs Ambient Temperature Bipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Frequency Bipolar Signal-toNoise a Distortion Ratio vs Input Source Impedance Bipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Unipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Spectral Response wi
PAGE 8
Test Circuits TL/H/10554 – 10 TL/H/10554–9 TL/H/10554 – 12 TL/H/10554–11 FIGURE 2.
PAGE 9
Timing Diagrams (Continued) Normal Conversion with Auto-Zero (CAL e 1, AZ e 0) TL/H/10554 – 14 Normal Conversion without Auto-Zero (CAL e 1, AZ e 1) TL/H/10554 – 15 9
PAGE 10
1.0 Pin Descriptions DVCC (28), AVCC (4) V b (5) DGND (14), AGND (3) VREF (2) The reference input voltage pin. To maintain accuracy the voltage at this pin should not exceed the AVCC or DVCC by more than 50 mV or go below 3.5 VDC. VIN (1) The analog input voltage pin. To guarantee accuracy the voltage at this pin should not exceed VCC by more than 50 mV or go below Vb by more than 50 mV. The Chip Select control input. This input is active low and enables the WR and RD functions.
PAGE 11
2.0 Functional Description (Continued) Digital Control Inputs A/D Function CS WR RD CAL AZ ß ß ß ß 1 0 ß 1 ß 1 X X 1 ß 1 ß X 1 1 1 1 1 ß 0 1 1 0 0 X X Start Conversion without Auto-Zero Read Conversion Result without Auto-Zero Start Conversion with Auto-Zero Read Conversion Result with Auto-Zero Start Calibration Cycle Test Mode (DB2, DB3, DB5 and DB6 become active) FIGURE 1.
PAGE 12
3.0 Analog Considerations (Continued) TL/H/10554 – 18 FIGURE 3. Analog Input Equivalent Circuit ductance tantalum capacitors of 10 mF or greater paralleled with 0.1 mF ceramic capacitors are recommended for supply bypassing. Separate bypass capacitors whould be placed b close to the DVCC, AVCC and V pins. If an unregulated voltage source is available in the system, a separate LM340LAZ-5.
PAGE 13
4.0 Dynamic Performance Power Supply Bypassing Many applications require the A/D converter to digitize ac signals, but the standard dc integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with ac input signals. The important specifications for ac applications reflect the converter’s ability to digitize ac signals without significant spectral errors and without adding noise to the digitized signal.
PAGE 14
ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold Physical Dimensions inches (millimeters) Order Number ADC1241CMJ, ADC1241CMJ/883, ADC1241BIJ or ADC1241CIJ NS Package Number J28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.