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TL/H/11017

ADC12441 Dynamically-Tested Self-Calibrating 12-Bit

Plus Sign A/D Converter with Sample-and-Hold

November 1994

ADC12441 Dynamically-Tested Self-Calibrating 12-Bit

Plus Sign A/D Converter with Sample-and-Hold

General Description

The ADC12441 is a CMOS 12-bit plus sign successive ap-

proximation analog-to-digital converter whose dynamic

specifications (S/N, THD, etc.) are tested and guaranteed.

On request, the ADC12441 goes through a self-calibration

cycle that adjusts positive linearity and full-scale errors to

less than

(/2 LSB each and zero error to less than

1 LSB. The ADC12441 also has the ability to go through

an Auto-Zero cycle that corrects the zero error during every

conversion.

The analog input to the ADC12441 is tracked and held by

the internal circuitry, and therefore does not require an ex-

ternal sample-and-hold. A unipolar analog input voltage

range (0V to

5V) or a bipolar range (

5V to

5V) can be

accommodated with

5V supplies.

The 13-bit word on the outputs of the ADC12441 gives a 2’s

complement representation of negative numbers. The digi-

tal inputs and outputs are compatible with TTL or CMOS

logic levels.

Features

Self-calibration provides excellent temperature stability

Internal sample-and-hold

Bipolar input range with single

5V reference

Applications

Digital signal processing

Telecommunications

Audio

High resolution process control

Instrumentation

Key Specifications

Resolution 12 bits plus sign

Conversion Time 13.8 ms (max)

Bipolar Signal/Noise 76.5 dB (min)

Total Harmonic Distortion

75 dB (max)

Aperture Time 100 ns

Aperture Jitter 100 ps

rms

Zero Error

1 LSB (max)

Positive Full Scale Error

1 LSB (max)

Power Consumption

5V 70 mW (max)

Sampling rate 55 kHz (max)

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

Simplified Block Diagram

TL/H/11017–1

Connection Diagram

Dual-In-Line Package

TL/H/11017–2

Top View

Order Number

ADC12441CMJ, ADC12441CMJ/883

or ADC12441CIJ

See NS Package Number J28A

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (14 pages)

PAGE 1
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold General Description Applications The ADC12441 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic specifications (S/N, THD, etc.) are tested and guaranteed. On request, the ADC12441 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than g (/2 LSB each and zero error to less than g 1 LSB.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Range ADC12441CIJ ADC12441CMJ, ADC12441CMJ/883 Supply Voltage (VCC e DVCC e AVCC) 6.5V b 6.5V Negative Supply Voltage (Vb) b 0.3V to (VCC a 0.3V) Voltage at Logic Control Inputs Voltage at Analog Inputs (VIN and VREF) (Vb b0.3V) to (VCC a 0.3V) 0.
PAGE 3
Converter Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, Analog Input Source Impedance e 600X, and fCLK e 2.0 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 4
Digital and DC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, and fCLK e 2.0 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) (Continued) Symbol IOUT Parameter TRI-STATEÉ Output Leakage Current Conditions Typical (Note 9) Limit (Notes 10, 19) Units (Limits) b 0.01 b3 mA (max) VOUT e 0V 0.
PAGE 5
AC Electrical Characteristics (Continued) Note 4: The power dissipation of this device under normal operation should never exceed 169 mW (Quiescent Power Dissipation a TTL Loads on the digital outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or outputs exceed the power supply).
PAGE 6
Electrical Characteristics (Continued) TL/H/11017 – 6 FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles TL/H/11017 – 7 FIGURE 1c.
PAGE 7
Typical Performance Characteristics (Continued) Linearity Error vs VREF Linearity Error vs Clock Frequency Full Scale Error Change vs Ambient Temperature Bipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Frequency Bipolar Signal-toNoise a Distortion Ratio vs Input Source Impedance Bipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Unipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Spectral Response wi
PAGE 8
Typical Performance Characteristics (Continued) Bipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 20 kHz Sine Wave Input TL/H/11017 – 11 TL/H/11017–10 Test Circuits TL/H/11017 – 13 TL/H/11017–12 TL/H/11017 – 15 TL/H/11017–14 FIGURE 2.
PAGE 9
Timing Diagrams (Continued) Normal Conversion with Auto-Zero (CAL e 1, AZ e 0) TL/H/11017 – 17 Normal Conversion without Auto-Zero (CAL e 1, AZ e 1) TL/H/11017 – 18 9
PAGE 10
1.0 Pin Descriptions DVCC (28), AVCC (4) V b (5) DGND (14), AGND (3) VREF (2) The reference input voltage pin. To maintain accuracy the voltage at this pin should not exceed the AVCC or DVCC by more than 50 mV or go below 3.5 VDC. VIN (1) The analog input voltage pin. To guarantee accuracy the voltage at this pin should not exceed VCC by more than 50 mV or go below Vb by more than 50 mV. The Chip Select control input. This input is active low and enables the WR and RD functions.
PAGE 11
2.0 Functional Description (Continued) Digital Control Inputs A/D Function CS WR RD CAL AZ ß ß ß ß 1 0 ß 1 ß 1 X X 1 ß 1 ß X 1 1 1 1 1 ß 0 1 1 0 0 X X Start Conversion without Auto-Zero Read Conversion Result without Auto-Zero Start Conversion with Auto-Zero Read Conversion Result with Auto-Zero Start Calibration Cycle Test Mode (DB2, DB3, DB5 and DB6 become active) FIGURE 1.
PAGE 12
3.0 Analog Considerations (Continued) with 0.1 mF ceramic capacitors are recommended for supply bypassing. Separate bypass capacitors whould be placed b close to the DVCC, AVCC and V pins. If an unregulated voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D’s VCC (and other analog circuitry) will greatly reduce digital noise on the supply line.
PAGE 13
4.0 Dynamic Performance to respond to the hold command. In the case of the ADC12441, the hold command is internally generated. When the Auto-Zero function is not being used, the hold command occurs at the end of the acquisition window, or seven clock periods after the rising edge of the WR. The delay between the internally generated hold command and the time that the ADC12441 actually holds the input signal is the aperture time. For the ADC12441, this time is typically 100 ns.
PAGE 14
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold Physical Dimensions inches (millimeters) Order Number ADC12441CMJ, ADC12441CMJ/883, or ADC12441CIJ NS Package Number J28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.