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TL/H/11876

ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter

with Input Multiplexer and Sample/Hold

December 1994

ADC12662

12-Bit, 1.5 MHz, 200 mW A/D Converter

with Input Multiplexer and Sample/Hold

General Description

Using an innovative multistep conversion technique, the

12-bit ADC12662 CMOS analog-to-digital converter digitizes

signals at a 1.5 MHz sampling rate while consuming a maxi-

mum of only 200 mW on a single

5V supply. The

ADC12662 performs a 12-bit conversion in three lower-res-

olution ‘‘flash’’ conversions, yielding a fast A/D without the

cost and power dissipation associated with true flash ap-

proaches.

The analog input voltage to the ADC12662 is tracked and

held by an internal sampling circuit, allowing high frequency

input signals to be accurately digitized without the need for

an external sample-and-hold circuit. The ADC12662 feature

two sample-and-hold/flash comparator sections which al-

low the converter to acquire one sample while converting

the previous. This pipelining technique increases conver-

sion speed without sacrificing performance. The multiplexer

output is available to the user in order to perform additional

external signal processing before the signal is digitized.

When the converter is not digitizing signals, it can be placed

in the Standby mode; typical power consumption in this

mode is 250 mW.

Features

Built-in sample-and-hold

Single

5V supply

Single channel or 2 channel multiplexer operation

Low Power Standby mode

Key Specifications

Sampling rate 1.5 MHz (min)

Conversion time 580 ns (typ)

Signal-to-Noise Ratio, f

100 kHz 67.5 dB (min)

Power dissipation (f

1.5 MHz) 200 mW (max)

No missing codes over temperature Guaranteed

Applications

Digital signal processor front ends

Instrumentation

Disk drives

Mobile telecommunications

Waveform digitizers

ADC12662 Block Diagram

TL/H/11876–1

Ordering Information

Industrial (

) Package

ADC12662CIV V44 Plastic Leaded Chip Carrier

ADC12662CIVF VGZ44A Plastic Quad Flat Package

ADC12062EVAL Evaluation Board

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Summary of content (20 pages)

PAGE 1
ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold General Description Features Using an innovative multistep conversion technique, the 12-bit ADC12662 CMOS analog-to-digital converter digitizes signals at a 1.5 MHz sampling rate while consuming a maximum of only 200 mW on a single a 5V supply.
PAGE 2
Absolute Maximum Ratings (Notes 1, 2) Soldering Information (Note 6) V Package, Infrared, 15 seconds If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
PAGE 3
Dynamic Characteristics (Note 10) The following specifications apply for DVCC e AVCC e a 5V, VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, RS e 25X, fIN e 100 kHz, 0 dB from fullscale, and fs e 1.5 MHz, unless otherwise specified. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C. Symbol Parameter Conditions Typ (Note 7) Limit (Note 8) Units (Limit) SINAD Signal-to-Noise Plus Distortion Ratio TMIN to TMAX 70 67.
PAGE 4
AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5V, VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, and fs e 1.5 MHz, unless otherwise specified. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C.
PAGE 5
Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints. Note 10: Dynamic testing of the ADC12662 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
PAGE 6
Typical Performance Characteristics Offset and Fullscale Error Change vs Reference Voltage Linearity Error Change vs Reference Voltage Mux ON Resistance vs Input Voltage Digital Supply Current vs Temperature Analog Supply Current vs Temperature Current Consumption in Standby Mode vs Voltage on Digital Input Pins Conversion Time (tCONV) vs Temperature EOC Delay Time (tEOC) vs Temperature Spectral Response SINAD vs Input Frequency (ADC In) SNR vs Input Frequency (ADC In) THD vs Input Frequency (ADC
PAGE 7
Typical Performance Characteristics SINAD vs Input Frequency (Through Mux) (Continued) SNR vs Input Frequency (Through Mux) SNR and THD vs Source Impedance THD vs Input Frequency (Through Mux) SNR and THD vs Reference Voltage TL/H/11876 – 7 7
PAGE 8
Timing Diagrams TL/H/11876 – 9 FIGURE 1. Interrupt Interface Timing (MODE e 0, OE e 1) TL/H/11876 – 10 FIGURE 2. High Speed Interface Timing (MODE e 0, OE e 1, CS e 0, RD e 0) TL/H/11876 – 13 FIGURE 3.
PAGE 9
Connection Diagrams TL/H/11876 – 15 TL/H/11876 – 29 Top View Top View Pin Descriptions AVCC DVCC AGND, DGND1, DGND2 DB0 – DB11 VIN1, VIN2 MUX OUT These are the two positive analog supply inputs. They should always be connected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed to AGND with a 0.1 mF ceramic capacitor in parallel with a 10 mF tantalum capacitor. ADC IN S0 This is the positive digital supply input.
PAGE 10
Pin Descriptions (Continued) OE VREF/16 This is the active high Output Enable control input. This pin can be thought of as an inverted version of the RD input (see Figure 6 ). Data output pins DB0–DB11 are TRI-STATE when OE is low. Data appears on DB0–DB11 only when OE is high and CS and RD are both low. This pin can be tied high. S/H This is the Sample/Hold control input. The analog input signal is held and a new conversion is initiated by the falling edge of this control input (when CS is low).
PAGE 11
Functional Description (Continued) Prior to a conversion, the Sample/Hold switch is closed, allowing the voltage on the S/H capacitor to track the input voItage. Switch 1 is in position 1. A conversion begins by opening the Sample/Hold switch and latching the output of the Voltage Estimator. The estimator decoder then selects two adjacent banks of tap points aIong the MSB ladder. These sixteen tap points are then connected to the sixteen flash converters.
PAGE 12
Functional Description (Continued) Applications Information The result of this second conversion is accurate to 10 bits and describes the input remainder as a voltage between two tap points (VH and VL) on the LSB ladder. To resolve the last two bits, the voltage across the ladder resistor (between VH and VL) is divided up into 4 equal parts by the capacitive voltage divider, shown in Figure 5.
PAGE 13
Applications Information (Continued) the maximum source impedance that will allow the input to settle to (/2 LSB (n e 13) at full speed is E 2.8 kX. To ensure (/2 LSB settling over temperature and device-to-device variation, RSOURCE should be a maximum of 500X when the converter is operated at full speed. If the signal source has a high output impedance, its output should be buffered with an operational amplifier capable of driving a switched 25 pF/100X load.
PAGE 14
Applications Information (Continued) TL/H/11876 – 20 FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp the overdrive currents into all pins must be less than 50 mA. When the input signal is expected to extend more than 300 mV beyond the power supply limits for any reason (unknown/uncontrollable input voltage range, power-on transients, fault conditions, etc.) some form of input protection, such as that shown in Figure 9, should be used.
PAGE 15
Applications Information (Continued) tional signal processing, such as filtering or gain, before the signal is returned to the ADC IN input and digitized. If no additional signal processing is required, the MUX OUT pin should be tied directly to the ADC IN pin. See Section 9.0 (APPLICATIONS) for a simple circuit that will alternate between the two inputs while converting at full speed. 3.
PAGE 16
Applications Information (Continued) The reference inputs are fully differential and define the zero to full-scale range of the input signal. They can be configured to span up to 5V (VREFb e 0V, VREF a e 5V), or they can be connected to different voltages (within the 0V to 5V limits) when other input spans are required. The ADC12662 is tested at VREFb (SENSE) e 0V, VREF a (SENSE) e 4.096V.
PAGE 17
Applications Information (Continued) 5.0 POWER SUPPLY CONSIDERATIONS The ADC12662 is designed to operate from a single a 5V power supply. There are two analog supply pins (AVCC) and one digital supply pin (DVCC). These pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee proper operation of the converter, all three supply pins should be connected to the same voltage source.
PAGE 18
Applications Information (Continued) converter is turned off, but other devices connected to it (op amps, microprocessors) still have power. Note that if there is no power to the converter, DGND e AGND e DVCC e AVCC e 0V, so all inputs should be within g 300 mV of AGND and DGND. Driving a high capacitance digital data bus. The more capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from DVCC and DGND.
PAGE 19
Applications Information (Continued) AC Coupling Bipolar Inputs TL/H/11876 – 28 Physical Dimensions inches (millimeters) Plastic Leaded Chip Carrier (V) Order Number ADC12662CIV NS Package Number V44A 19
PAGE 20
ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flat Package (VF) Order Number ADC12662CIVF NS Package Number VGZ44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.