User Manual

Functional Description (Continued)
The resistor string near the center of the block diagram in
Figure 4 generates the 6-bit and 10-bit reference voltages
for the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to (/1024 of the total string resist-
ance. These resistors form the LSB Ladder* and have a
voltage drop of (/1024 of the total reference voltage (V
REF
a
b
V
REF
b
) across each of them. The remaining resistors
form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has (/8 of the total reference voltage across
it. Within a given MSB ladder section, each of the eight MSB
resistors has (/64 of the total reference voltage across it. Tap
points are found between all of the resistors in both the
MSB and LSB ladders. The Comparator MultipIexer can
connect any of these tap points, in two adjacent groups of
eight, to the sixteen comparators shown at the right of
Fig-
ure 4.
This function provides the necessary reference volt-
ages to the comparators during the first two flash conver-
sions.
*Note: The weight of each resistor on the LSB ladder is actually equivalent
to four 12-bit LSBs. It is called the LSB ladder because it has the
highest resolution of all the ladders in the converter.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of
Figure 4 form
the Voltage Estimator. The Estimator DAC, connected be-
tween V
REF
a
and V
REF
b
, generates the reference volt-
ages for the six Voltage Estimator comparators. The com-
parators perform a very low resoIution A/D conversion to
obtain an ‘‘estimate’’ of the input voltage. This estimate is
used to control the placement of the Comparator Multiplex-
er, connecting the appropriate MSB ladder section to the
sixteen flash comparators. A total of only 22 comparators (6
in the Voltage Estimator and 16 in the flash converter) is
required to quantize the input to 6 bits, instead of the 64 that
would be required using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed,
allowing the voltage on the S/H capacitor to track the input
voItage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points aIong the MSB ladder.
These sixteen tap points are then connected to the sixteen
flash converters. For exampIe, if the input voltage is be-
tween ±/16 and -/16 of V
REF
(V
REF
e
V
REF
a
b
V
REF
b
), the
estimator decoder instructs the comparator multiplexer to
select the sixteen tap points between )/8 and %/8 (%/16 and
`/16)ofV
REF
and connects them to the sixteen flash con-
verters. The first flash conversion is now performed, produc-
ing the first 6 MSBs of data.
At this point, Voltage Estimator errors as large as (/16 of
V
REF
will be corrected since the flash converters are con-
nected to ladder voltages that extend beyond the range
specified by the Voltage Estimator. For example, if
(-/16)V
REF
k
V
IN
k
('/16)V
REF
, the Voltage Estimator’s com-
parators tied to the tap points below ('/16)V
REF
will output
‘‘1’’s (000111). This is decoded by the estimator decoder to
‘‘10’’. The 16 comparators will be placed on the MSB ladder
tap points between (*/8)V
REF
and (±/8)V
REF
. This overlap of
((/16)V
REF
will automatically cancel a Voltage Estimator er-
ror of up to 256 LSBs. If the first flash conversion deter-
mines that the input voltage is between (*/8)V
REF
and
((%/8)V
REF
b
LSB/2), the Voltage Estimator’s output code
will be corrected by subtracting ‘‘1’’, resulting in a corrected
value of ‘‘01’’ for the first two MSBs. If the first flash conver-
sion determines that the input voltage is between
(%/8)V
REF
b
LSB/2) and (±/8)V
REF
, the voltage estimator’s
output code is unchanged.
The results of the first flash and the Voltage Estimator’s
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap. This code is convert-
ed to a voltage by the Correction DAC. To generate the next
four bits, SW1 is moved to position 2, so the ladder
voltage and the correction voltage are subtracted from the
input voltage. The remainder is applied to the sixteen flash
converters and compared with the 16 tap points from the
LSB ladder.
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