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TL/H/11830

ADC12L030/ADC12L032/ADC12L034/ADC12L038

3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

March 1995

ADC12L030/ADC12L032/ADC12L034/ADC12L038

3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O

A/D Converters with MUX and Sample/Hold

General Description

The ADC12L030 family is 12-bit plus sign successive ap-

proximation A/D converters with serial I/O and configurable

input multiplexers. These devices are fully tested with a sin-

gle 3.3V power supply. The ADC12L032, ADC12L034 and

ADC12L038 have 2, 4 and 8 channel multiplexers, respec-

tively. Differential multiplexer outputs and A/D inputs are

available on the MUXOUT1, MUXOUT2, A/DIN1 and

A/DIN2 pins. The ADC12L030 has a two channel multiplex-

er with the multiplexer outputs and A/D inputs internally

connected. On request, these A/Ds go through a self cali-

bration process that adjusts linearity, zero and full-scale er-

rors to less than

(/2 LSB each.

The analog inputs can be configured to operate in various

combinations of single-ended, differential, or pseudo-differ-

ential modes. A fully differential unipolar analog input range

(0V to

3.3V) can be accommodated with a single

3.3V

supply. In the differential modes, valid outputs are obtained

even when the negative inputs are greater than the positive

because of the 12-bit plus sign two’s compliment output

data format.

The serial I/O is configured to comply with NSC’s MICRO-

WIRE

and Motorola’s SPI standards. For complementary

voltage references see the LM4040, LM4041 or LM9140

data sheets.

Applications

Portable Medical instruments

Portable computing

Portable Test equipment

Features

0V to 3.3V analog input range with single 3.3V power

supply

Serial I/O (MICROWIRE and SPI Compatible)

2, 4, or 8 channel differential or single-ended

multiplexer

Analog input sample/hold function

Power down mode

Variable resolution and conversion rate

Programmable acquisition time

Variable digital output word length and format

No zero or full scale adjustment required

Fully tested and guaranteed with a 2.5V reference

No Missing Codes over temperature

Key Specifications

Resolution 12-bit plus sign

12-bit plus sign conversion time 8.8 ms (min)

12-bit plus sign sampling rate 73 kHz (max)

Integral linearity error

1 LSB (max)

Single supply 3.3V

10%

Power dissipation 15 mW (max)

Ð Power down 40 mW (typ)

ADC12L038 Simplified Block Diagram

TL/H/11830– 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

COPS

microcontrollers, HPC

and MICROWIRE

are trademarks of National Semiconductor Corporation.

Microsoft

is a trademark of Microsoft Corporation.

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Summary of content (40 pages)

PAGE 1
ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description Features The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. These devices are fully tested with a single 3.3V power supply. The ADC12L032, ADC12L034 and ADC12L038 have 2, 4 and 8 channel multiplexers, respectively.
PAGE 2
Connection Diagrams 20-Pin Dual-In-Line and Wide Body SO Packages 16-Pin Dual-In-Line and Wide Body SO Packages TL/H/11830–2 Top View Top View 28-Pin Dual-In-Line and Wide Body SO Packages 24-Pin Dual-In-Line and Wide Body SO Packages Top View TL/H/11830 – 3 TL/H/11830–4 Top View Ordering Information Industrial Temperature Range b 40§ C s TA s a 85§ C NS Package Number ADC12L030CIN N16E ADC12L030CIWM M16B ADC12L032CIN N20A ADC12L032CIWM M20B ADC12L034CIN N24C ADC12L034CIWM M24B ADC1
PAGE 3
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) Operating Temperature Range TMIN s TA s TMAX ADC12L030CIN, ADC12L030CIWM, ADC12L032CIN, ADC12L032CIWM, ADC12L034CIN, ADC12L034CIWM, ADC12L038CIN, b 40§ C s TA s a 85§ C ADC12L038CIWM If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Positive Supply Voltage (V a e VA a e VD a ) 6.
PAGE 4
Converter Electrical Characteristics (Continued) The following specifications apply for V a e VA a e VD a e a 3.3 VDC, VREF a e a 2.500 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 5 MHz, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 5
Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 3.3 VDC, VREF a e a 2.500 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 5 MHz, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 6
DC and Logic Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 3.3 VDC, VREF a e a 2.500 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, fCK e fSK e 5 MHz, RS e 25X, source impedance for VREF a and VREFb s 25X, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 7
AC Electrical Characteristics The following specifications apply for V a e VA a e VD a e a 3.3 VDC, VREF a e a 2.500 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, tr e tf e 3 ns, fCK e fSK e 5 MHz, RS e 25X, source impedance for VREF a and VREFb s 25X, fullydifferential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 8
AC Electrical Characteristics (Continued) The following specifications apply for V a e VA a e VD a e a 3.3 VDC, VREF a e a 2.500 VDC, VREFb e 0 VDC, 12-bit a sign conversion mode, tr e tf e 3 ns, fCK e fSK e 5 MHz, RS e 25X, source impedance for VREF a and VREFb s 25X, fullydifferential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 9
Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
PAGE 10
Electrical Characteristics (Continued) TL/H/11830 – 7 FIGURE 1a. Transfer Characteristic TL/H/11830 – 8 FIGURE 1b.
PAGE 11
Electrical Characteristics (Continued) TL/H/11830 – 9 FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle TL/H/11830 – 10 FIGURE 2.
PAGE 12
Typical Performance Characteristics The following curves apply for 12-bit a sign mode after auto-calibration unless otherwise specified. The performance for 8-bit a sign mode is equal to or better than shown.
PAGE 13
Test Circuits DO ‘‘TRI-STATE’’ (t1H, t0H) DO except ‘‘TRI-STATE’’ TL/H/11830 – 15 TL/H/11830 – 16 Leakage Current TL/H/11830 – 17 Timing Diagrams DO Falling and Rising Edge DO ‘‘TRI-STATE’’ Falling and Rising Edge TL/H/11830 – 18 TL/H/11830 – 19 DI Data Input Timing TL/H/11830 – 20 13
PAGE 14
Timing Diagrams (Continued) DO Data Output Timing Using CS TL/H/11830 – 21 DO Data Output Timing with CS Continuously Low TL/H/11830 – 22 ADC12L038 Auto Cal or Auto Zero TL/H/11830 – 23 Note: DO output data is not valid during this cycle.
PAGE 15
Timing Diagrams (Continued) ADC12L038 Read Data without Starting a Conversion Using CS TL/H/11830 – 24 ADC12L038 Read Data without Starting a Conversion with CS Continuously Low TL/H/11830 – 25 15
PAGE 16
Timing Diagrams (Continued) ADC12L038 Conversion Using CS with 8-Bit Digital Output Format TL/H/11830 – 26 ADC12L038 Conversion Using CS with 16-Bit Digital Output Format TL/H/11830 – 27 16
PAGE 17
Timing Diagrams (Continued) ADC12L038 Conversion with CS Continuously Low and 8-Bit Digital Output Format TL/H/11830 – 28 ADC12L038 Conversion with CS Continuously Low and 16-Bit Digital Output Format TL/H/11830 – 29 17
PAGE 18
Timing Diagrams (Continued) ADC12L038 Software Power Up/Down Using CS with 16-Bit Digital Output Format TL/H/11830 – 30 ADC12L038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format TL/H/11830 – 31 18
PAGE 19
Timing Diagrams (Continued) ADC12L038 Hardware Power Up/Down TL/H/11830 – 32 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register.
PAGE 20
Pin Descriptions CCLK SCLK DI DO EOC CS maturely ended. The data in the output latches may be corrupted. Therefore, when CS is brought back low during a conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied, it expects to see 13 clock pulses for each I/O sequence.
PAGE 21
Pin Descriptions (Continued) VREF a This is the positive analog voltage reference input. In order to maintain accuracy the voltage range of VREF (VREF e VREF a b VREFb) is 1 VDC to 3.3 VDC and the voltage at VREF a cannot exceed VA a . See Figure 4 for recommended bypassing. VREFb The negative voltage reference input. In order to maintain accuracy the voltage at this pin must not go below GND or exceed VA a . (See Figure 4 ). VA a , VD a These are the analog and digital power supply pins.
PAGE 22
Tables TABLE I.
PAGE 23
Tables (Continued) TABLE III.
PAGE 24
Tables (Continued) TABLE V.
PAGE 25
Tables (Continued) TABLE VII. Status Register Status Bit Location DB0 Status Bit PU DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 PD Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test Mode When ‘‘High’’ the conversion result will be output MSB first. When ‘‘Low’’ the result will be output LSB first. When ‘‘High’’ the device is in test mode. When ‘‘Low’’ the device is in user mode.
PAGE 26
Application Hints (Continued) sary to be input to the ADC to accomplish this configuration modification. The next instruction, shown in Figure 6 , issued to the A/D starts conversion N a 1 with 8 bits of resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N. The number of SCLKs applied to the A/D during any conversion I/O sequence should vary in accord with the data out word format chosen during the previous conversion I/O sequence.
PAGE 27
Application Hints (Continued) The following table lists the instructions required to return the device to user mode: 4 Differential Channels 8 Single-Ended Channels with COM as Zero Reference DI Data Instruction DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 TEST MODE H X X X H H H H RESET L L L L H H H L TEST MODE L L L L H L H L INSTRUCTIONS L L L L H L H H USER MODE L L L L H H H H Power Up L L L L H L H L Set DO with or without Sign H or L L L L H H L
PAGE 28
Application Hints (Continued) TL/H/11830 – 46 FIGURE 9. Single-Ended Biasing 5 MHz CCLK frequency) would allow the 600X to increase to 6k, which with a 1 mF coupling capacitor would set the high pass corner at 26 Hz. The value of R1 will depend on the value of R2. An alternative method for biasing pseudo-differential operation is to use the a 2.5V from the LM9140 to bias any amplifier circuits driving the ADC as shown in Figure 11. The value of the resistor pull-up biasing the LM9140-2.
PAGE 29
Application Hints (Continued) TL/H/11830 – 48 FIGURE 11. Alternative Pseudo-Differential Biasing TL/H/11830 – 50 FIGURE 12. Fully Differential Biasing The ADC12L030/2/4/8 can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input voltage is proportional to the voltage used for the ADC’s reference voltage. When this voltage is the system power supply, the VREF a pin is connected to VA a and VREFb is connected to ground. This technique relaxes the 3.
PAGE 30
Application Hints (Continued) system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs.
PAGE 31
Application Hints (Continued) ple, operating with a resolution of 12 Bits a sign, a 5 MHz clock frequency and maximum acquistion time of 34 conversion clock periods the ADC’s analog inputs can handle a source impedance as high as 6 kX. The acquisition time may also be extended to compensate for the settling or response time of external circuitry connected between the MUXOUT and A/DIN pins.
PAGE 32
Application Hints (Continued) An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N a D) and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained.
PAGE 33
Application Hints (Continued) to the ADC12L038’s DI, SCLK, and DO pins, respectively. The D flip flop drive the CS control line. 15.0 AN RS232 SERIAL INTERFACE Shown below is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR, RTS, and CTS RS232 signal lines are buffered via level translators and connected TL/H/11830 – 45 Note: VA a , VD a , and VREF a on the ADC12L038 each have 0.01 mF and 0.1 mF chip caps, and 10 mF tantalum caps. All logic devices are bypassed with 0.1 mF caps.
PAGE 34
Application Hints (Continued) ’variables DOL4Data Out word length, DI4Data string ’ DO4A/D result string ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS OUT &H3FC, (&HFE AND INP (&H3FC)) ’SET DTR OUT &H3FC, (&HFD AND INP (&H3FC)) ’SET RTS for A/D DI input, HIGH LOW LOW OUT &H3FC, (&HEF AND INP (&H3FC)) ’set B4 low 10 LINE INPUT ‘DI data for ADC12038 (see Mode Table on data sheet)‘; DI$ INPUT ‘ADC12038 output word length (8,9,12,13,16 or 17)‘; DOL 20 ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) OU
PAGE 35
PAGE 36
Physical Dimensions inches (millimeters) Order Number ADC12L030CIWM NS Package Number M16B Order Number ADC12L032CIWM NS Package Number M20B 36
PAGE 37
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12L034CIWM NS Package Number M24B Order Number ADC12L038CIWM NS Package Number M28B 37
PAGE 38
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12L030CIN NS Package Number N16E Order Number ADC12L032CIN NS Package Number N20A 38
PAGE 39
Physical Dimensions inches (millimeters) (Continued) Order Number ADC12L034CIN NS Package Number N24C 39
PAGE 40
ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold Physical Dimensions inches (millimeters) (Continued) Order Number ADC12L038CIN NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.