ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold General Description Features The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS.
ADC12L066 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12L066CIVY 32 Pin LQFP ADC12L066CIVYX 32 Pin LQFP Tape and Reel ADC12L066EVAL Evaluation Board Block Diagram 20032802 www.national.
ADC12L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ 3 VIN− 1 VREF 31 VRP 32 VRM 30 VRN Analog signal Input pins. With a 1.0V reference voltage the differential input signal level is 2.0 VP-P. The VIN- pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. VREF is 1.
ADC12L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol 14–19, 22–27 D0–D11 Equivalent Circuit (Continued) Description Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.
Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) VA, VD, VDR Package Dissipation at TA = 25˚C −0.05V to (VD + 0.05V) VIN Input −0V to (VA − 0.5V) VCM 0.5V to (VA -1.5V) ≤100 mV |AGND–DGND| ± 25 mA ± 50 mA Package Input Current (Note 3) 0.8V to 1.5V CLK, PD, OE −0.3V to (VA or VD +0.
ADC12L066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) 64.6 dB (min) 65 dB (min) 64.
(Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions fIN = 10 MHz, VIN = −0.5 dBFS 85˚C 25˚C fIN = 25 MHz, VIN = −0.
ADC12L066 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions fIN = 10 MHz, VIN = −0.
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
ADC12L066 OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
ADC12L066 Timing Diagram 20032809 Output Timing Transfer Characteristic 20032810 FIGURE 1. Transfer Characteristic 11 www.national.
ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. DNL DNL vs. fCLK 200328E6 20032891 DNL vs. Clock Duty Cycle DNL vs. Temperature 20032892 20032893 INL INL vs. fCLK 200328E7 www.national.
INL vs. Clock Duty Cycle INL vs. Temperature 20032895 20032896 SNR vs. VA SNR vs. VDR 20032897 20032898 SNR vs. VCM SNR vs. fCLK 200328B1 200328B2 13 www.national.com ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SNR vs. Clock Duty Cycle SNR vs. VREF 200328B3 200328B4 SNR vs. Temperature THD vs. VA 200328B5 200328B6 THD vs. VDR THD vs. VCM 200328B7 www.national.
THD vs. Clock Duty Cycle THD vs. fCLK 200328C1 200328B9 THD vs. VREF THD vs. Temperature 200328C3 200328C2 SINAD vs. VA SINAD vs. VDR 200328C4 200328C5 15 www.national.com ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SINAD vs. fCLK SINAD vs. VCM 200328C6 200328C7 SINAD vs. Clock Duty Cycle SINAD vs. VREF 200328C8 200328C9 SINAD vs. Temperature SFDR vs. VA 200328D1 www.national.
SFDR vs. VCM SFDR vs. VDR 200328D3 200328D4 SFDR vs. fCLK SFDR vs. Clock Duty Cycle 200328D6 200328D5 SFDR vs. VREF SFDR vs. Temperature 200328D8 200328D7 17 www.national.com ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) tOD vs. VDR Power Consumption vs. fCLK 200328D9 200328E1 Spectral Response @ 10 MHz Input Spectral Response @ 25 MHz Input 200328E4 200328E8 Spectral Response @ 50 MHz Input Spectral Response @ 75MHz Input 200328E9 www.national.
Spectral Response @ 100 MHz Input Spectral Response @ 150 MHz Input 200328J1 200328J2 Spectral Response @ 240 MHz Input 200328E5 19 www.national.com ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated.
ADC12L066 1.1 ANALOG INPUTS Functional Description The ADC12L066 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There is one reference input pin, VREF. Operating on a single +3.3V supply, the ADC12L066 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 12 bits.
Relationship–Differential Input and Table 2. Input to Output Relationship–Single-Ended Input indicate the input to output relationship of the ADC12L066. (Continued) The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency (sine wave) inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion. 1.3.
ADC12L066 Applications Information Since ADC noise increases with increased output capacitance at the digital output pins, do use the TRI-STATE outputs of the ADC12L066 to drive a bus. Rather, each output pin should be located close to and drive a single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output pin, located close to their respective pins, should be added to the circuit. See Section 3.0. (Continued) 2.
ADC12L066 Applications Information (Continued) 20032813 FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer 20032814 FIGURE 5. Differential Drive Circuit of Figure 4 23 www.national.
ADC12L066 Applications Information (Continued) 20032815 FIGURE 6. Driving the Signal Inputs with a Transformer The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12L066’s other ground pins.
other digital lines. Even the generally accepted 90˚ crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path.
ADC12L066 Applications Information Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. (Continued) cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g.
inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC12L066CIVY NS Package Number VBE32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
