Instruction Manual

Applications Information (Continued)
tween the converter’s input pins and ground or to the refer-
ence input pin and ground should be connected to a very
clean point in the ground plane.
Figure 7 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. Furthermore, all components in the reference
circuitry and the input signal chain that are connected to
ground should be connected together with short traces and
enter the ground plane at a single point. All ground connec-
tions should have a low inductance path to ground.
Best performance will be obtained with a single ground plane
and separate analog and digital power planes. The power
planes define analog and digital board areas of the board.
Analog and digital components and signal lines should be
kept within their own areas.
7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. The maximum
allowable jitter to avoid the addition of noise to the conver-
sion process is
Max Jitter=1/(2
n+1
x π xf
IN
)
Isolate the ADC clock from any digital circuitry with buffers,
as with the clock tree shown in Figure 8. To avoid adding
jitter to the clock signal, the elements of Figure 8 should be
capable of toggling at a up to ten times the frequency used.
As mentioned in Section 6.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12L080 with
a device that is powered from supplies outside the range of
the ADC12L080 supply. Such practice may lead to conver-
sion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
DR
and DR GND. These large charging cur-
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the PC board will
reduce this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t
OD
to increase, making it difficult to properly latch
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12L080, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.2, the sampling input is difficult to
drive without degrading dynamic performance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor at each amplifier output and a
capacitor at each of the ADC analog inputs to ground (as
shown in Figure 5 and Figure 6) will improve performance.
The LMH6702, LMH6628, LMH6622 and LMH6655 have
been successfully used to drive the analog inputs of the
ADC12L080.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
o
out of phase
with each other. Board layout, including equality of the length
of the two traces to the input pins, will affect the effective
phase between these two signals. Remember that an opera-
tional amplifier operated in the non-inverting configuration
will exhibit more time delay than will the same device oper-
ating in the inverting configuration.
Operating with the reference pins outside of the speci-
fied range. As mentioned in Section 2.1, V
REF
should be in
the range specified in the Operating Ratings table. Operating
outside of these limits could lead to performance degrada-
tion.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
20061017
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
ADC12L080
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