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Features

• Low-voltage Operation

– 2.7 (V

= 2.7V to 5.5V)

• Internally Organized 131,072 x 8

• 2-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 400 kHz (2.7V) and 1 MHz (5V) Clock Rate

• Write Protect Pin for Hardware and Software Data Protection

• 256-byte Page Write Mode (Partial Page Writes Allowed)

• Random and Sequential Read Modes

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

– Endurance: 100,000 Write Cycles/Page

– Data Retention: 40 Years

• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA

Packages

Description

The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-

mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The

device’s cascadable feature allows up to 2 devices to share a common 2-wire bus.

The device is optimized for use in many industrial and commercial applications where

low-power and low-voltage operation are essential. The devices are available in

space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP), and 8-ball

dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)

versions.

2-wire Serial

EEPROM

1M (131,072 x 8)

AT24C1024

Advance

Information

Rev. 1471D–07/01

Pin Configurations

Pin Name Function

A1 Address Input

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-lead PDIP

GND

VCC

SCL

SDA

8-lead Leadless Array

Bottom View

VCC

SCL

SDA

GND

8-lead SOIC

GND

VCC

SCL

SDA

8-ball dBGA

Bottom View

VCC

SCL

SDA

GND

Summary of content (16 pages)

PAGE 1
Features • Low-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) Internally Organized 131,072 x 8 2-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 400 kHz (2.
PAGE 2
Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
AT24C1024 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices.
PAGE 4
Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V. Symbol Test Condition CI/O Input/Output Capacitance (SDA) CIN Note: Max Units Conditions 8 pF VI/O = 0V 6 pF VIN = 0V Input Capacitance (A1, SCL) 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V, TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted).
PAGE 5
AT24C1024 AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. Symbol Parameter Test Conditions Min fSCL Clock Frequency, SCL 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V tLOW Clock Pulse Width Low 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 0.6 1.3 µs tHIGH Clock Pulse Width High 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 0.4 1.0 µs tAA Clock Low to Data Out Valid 4.5V ≤ VCC ≤ 5.
PAGE 6
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
PAGE 7
AT24C1024 Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) (1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
PAGE 8
Data Validity Start and Stop Definition Output Acknowledge 8 AT24C1024 1471D–07/01
PAGE 9
AT24C1024 Device Addressing The 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices. The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus. The A1 bit must compare to the corresponding hardwired input pin.
PAGE 10
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page, to the first byte of the first page.
PAGE 11
AT24C1024 Figure 1. Device Address 0 Figure 2. Byte Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 3. Page Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 4.
PAGE 12
Figure 5. Random Read P 0 Figure 6.
PAGE 13
AT24C1024 Ordering Information tWR (max) (ms) ICC (max) (µA) 2000 ISB (max) (µA) 3.0 fMAX (kHz) Package Operation Range 400 AT24C1024-10CC-2.7 AT24C1024C1-10CC-2.7 AT24C1024-10PC-2.7 AT24C1024W-10SC-2.7 AT24C1024-10UC-2.7 8C 8C1 8P3 8S2 8U8 Commercial (0°C to 70°C) 400 AT24C1024-10CI-2.7 AT24C1024C1-10CI-2.7 AT24C1024-10PI-2.7 AT24C1024W-10SI-2.7 AT24C1024-10UI-2.7 8C 8C1 8P3 8S2 8U8 Industrial (-40°C to 85°C) 10 2000 3.0 Ordering Code Package Type 8C 8-lead, 0.
PAGE 14
Packaging Information 8C, 8-lead, 0.230" Wide, Leadless Array Package (LAP) Dimensions in Millimeters and (Inches)* 8C1, 8-lead 0.300" Wide, Leadless Array Package (LAP) Dimensions in Millimeters and (Inches)* SIDE VIEW TOP VIEW SIDE VIEW TOP VIEW 5.10 (0.201) 4.90 (0.193) 5.03 (0.198) 4.83 (0.190) 1.32 (0.052) 1.22 (0.048) 6.09 (0.240) 5.89 (0.232) 1.14 (0.045) 0.94 (0.037) 8.10 (0.319) 7.90 (0.311) 1.14 (0.045) 0.94 (0.037) BOTTOM VIEW 0.38 (0.015) 0.30 (0.012) BOTTOM VIEW 0.38 (0.015) 0.
PAGE 15
AT24C1024 Packaging Information 8U8, 8-ball, die Ball Grid Array Package (dBGA) Dimensions in Millimeters and (Inches) TOP VIEW 2.85 (0.112) 3.84 (0.151) SIDE VIEW 0.90 (0.035) BOTTOM VIEW 8 1 7 2 6 3 5 4 0.75 (0.029) 0.80 (0.031) 0.75 (0.029) 1.05 (0.041) 0.38 (0.
PAGE 16
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