Features • Single 2.3V - 3.6V or 2.7V - 3.
The physical sectoring and the erase block sizes of the AT25DF041A have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently.
AT25DF041A 2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Asserted State Type Low Input Symbol Name and Function CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.
3. Block Diagram CONTROL AND PROTECTION LOGIC CS SI SO SRAM DATA BUFFER INTERFACE CONTROL AND LOGIC ADDRESS LATCH SCK I/O BUFFERS AND LATCHES WP Y-DECODER Y-GATING X-DECODER FLASH MEMORY ARRAY 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four levels of granularity including a full chip erase.
AT25DF041A Memory Architecture Diagram Block Erase Detail 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) 16KB (Sector 10) 32KB 8KB (Sector 9) 8KB (Sector 8) 64KB 32KB (Sector 7) 32KB 32KB 64KB (Sector 6) 64KB ••• ••• ••• 32KB 32KB 64KB (Sector 0) 64KB 32KB 4KB Block Erase (20h Command) 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Block Address Range 07F F F F h – 07E F F F h – 07DF F F h – 0
5. Device Operation The AT25DF041A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF041A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
AT25DF041A Table 6-1.
7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device.
AT25DF041A 8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh).
The Byte/Page Program mode is the default programming mode after the device powers-up or resumes from a device reset. Figure 8-1. Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 1 0 MSB A A A A A A A A D MSB D D D D D D D MSB HIGH-IMPEDANCE SO Figure 8-2.
AT25DF041A device. Deasserting the CS pin will start the internally self-timed program operation, and the byte of data will be programmed into the memory location specified by A23 - A0. After the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next byte of data. When the CS pin is deasserted, the second byte of data will be programmed into the next sequential memory location.
Figure 8-3. Sequential Program Mode – Status Register Polling CS Status Register Read Seqeuntial Program Mode Command Command Seqeuntial Program Mode Command SI Opcode A23-16 A15-8 A7-0 Data 05h Opcode Data Seqeuntial Program Mode Write Disable Command Command 05h Opcode Data 04h 05h First Address to Program STATUS REGISTER DATA STATUS REGISTER DATA STATUS REGISTER DATA HIGH-IMPEDANCE SO Note: Each transition Figure 8-4.
AT25DF041A If the address specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18 through 15) at one time.
8.4 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably.
AT25DF041A 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed.
Figure 9-2. Write Disable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 0 0 MSB SO 9.3 HIGH-IMPEDANCE Protect Sector Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up or after a device reset, each Sector Protection Register will default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased.
AT25DF041A Figure 9-3. Protect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 0 ADDRESS BITS A23-A0 1 1 0 MSB SO 9.4 A A A A A A A A A A A A MSB HIGH-IMPEDANCE Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection Register values).
9.5 Global Protect/Unprotect The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect certain sectors as needed.
AT25DF041A Table 9-2. WP State Valid SPRL and Global Protect/Unprotect Conditions Current SPRL Value New Write Status Register Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 0 Protection Operation New SPRL Value Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection.
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the Sector Protection Registers).
AT25DF041A 9.7 Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met – the WP pin must be asserted and the SPRL bit must be in the logical “1” state.
Table 9-5. WP 0 0 1 1 22 Hardware and Software Locking SPRL Locking 0 1 Hardware Locked 0 1 Software Locked SPRL Change Allowed Sector Protection Registers Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed.
AT25DF041A 10. Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.
10.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be performed.
AT25DF041A 10.1.6 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset.
10.2 Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
AT25DF041A 11. Other Commands and Functions 11.1 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
Figure 11-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI SO 9Fh HIGH-IMPEDANCE Note: Each transition 11.
AT25DF041A Figure 11-2. Deep Power-down CS tEDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 1 1 0 0 1 MSB SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current 11.3 Deep Power-Down Mode Current Resume from Deep Power-down In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down command is the only command that the device will recognize while in the Deep Power-down mode.
11.4 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted.
AT25DF041A 12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C *NOTICE: Storage Temperature..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V 12.
12.4 AC Characteristics AT25DF041A (2.3V version) Symbol Parameter fSCK Serial Clock (SCK) Frequency fRDLF SCK Frequency for Read Array (Low Frequency - 03h opcode) tSCKH SCK High Time 8.0 6.4 ns SCK Low Time 8.0 6.4 ns SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.
AT25DF041A 12.5 Program and Erase Characteristics Symbol Parameter tPP(1) Page Program Time (256 Bytes) tBP Byte Program Time tBLKE(1) tCHPE Chip Erase Time (2) Write Status Register Time Typ Max Units 1.2 5 ms 7 Block Erase Time (1)(2) tWRSR Note: Min µs 4 Kbytes 50 200 32 Kbytes 250 600 64 Kbytes 400 950 3 7 sec 200 ns ms 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles. 2.
13. Waveforms Figure 13-1. Serial Input Timing tCSH CS tCSLH tSCKL tCSLS tSCKH tCSHH tCSHS SCK tDS SI SO tDH MSB LSB MSB HIGH-IMPEDANCE Figure 13-2. Serial Output Timing CS tSCKH tSCKL tDIS SCK SI tOH tV tV SO Figure 13-3.
AT25DF041A Figure 13-4. HOLD Timing – Serial Output CS SCK tHHH tHLS tHLH tHHS HOLD SI tHLQZ tHHQX SO Figure 13-5.
14. Ordering Information 14.1 Ordering Code Detail AT 2 5DF 0 4 1A– SSHF –B Designator Shipping Carrier Option B = Bulk (tubes) Y = Trays T = Tape and reel Product Family Operating Voltage Blank = 2.7V minimum (2.7V to 3.6V) F = 2.3V minimum (2.3V to 3.6V) Device Density Device Grade 04 = 4-megabit H = Green, NiPdAu lead finish, industrial temperature range (-40°C to +85°C) Interface Package Option M = 8-pad, 5 x 6 x 0.6 mm UDFN SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.
AT25DF041A 15. Packaging Information 15.1 8MA1 – UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A E2 K 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 2 e D2 6 3 5 4 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C b BOTTOM VIEW L NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.
15.2 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
AT25DF041A 15.3 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW MAX NOM NOTE A 1.70 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° e Notes: 1. 2. 3. 4. MIN 2.16 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
16. Revision History Revision Level – Release Date History A – March 2007 Initial release. B – November 2007 Changed part number ordering code to reflect NiPdAu lead finish. - Changed AT25DF041A-SSU to AT25DF041A-SSH. - Changed AT25DF041A-SU to AT25DF041A-SH. - Changed AT25DF041A-MU to AT25DF041A-MH. Added lead finish details to Ordering Information table. Added 2.3V - 3.6V operating range. Changed 8M1-A MLF package to 8MA1 UDFN package. Added Ordering Code Detail.
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