Manual

AT25DQ161 [DATASHEET]

8671C–DFLASH–11/2012

4. Memory Array

To provide the greatest flexibility, the memory array of the AT25DQ161 can be erased in four levels of granularity

including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each

sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for

both code and data storage applications, allowing both code and data segments to reside in their own isolated regions.

The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each

physical sector.

Figure 4-1. Memory Architecture Diagram

256 bytes