Features • Single 2.7V - 3.
The AT26DF081A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected.
AT26DF081A 2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Asserted State Type Low Input Symbol Name and Function CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.
Figure 2-1. CS SO WP GND 8-SOIC Top View 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 3. Block Diagram CONTROL AND PROTECTION LOGIC CS SI SO SRAM DATA BUFFER INTERFACE CONTROL AND LOGIC ADDRESS LATCH SCK I/O BUFFERS AND LATCHES WP Y-DECODER Y-GATING X-DECODER FLASH MEMORY ARRAY 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four levels of granularity including a full chip erase.
AT26DF081A Memory Architecture Diagram Block Erase Detail 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) 32KB (Sector 18) 8KB (Sector 17) 8KB (Sector 16) 32KB 64KB 32KB 16KB (Sector 15) 32KB 64KB (Sector 14) 64KB ••• ••• ••• 32KB 32KB 64KB (Sector 0) 64KB 32KB 4KB Block Erase (20h Command) 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Block Address Range 0FFFFFh 0FEFFFh 0FDFFFh 0FCFFFh 0FBFFFh
5. Device Operation The AT26DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
AT26DF081A Table 6-1.
7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device.
AT26DF081A Figure 7-2. Read Array – 03h Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB 1 1 A A A A A A A A A MSB DATA BYTE 1 HIGH-IMPEDANCE SO D MSB D D D D D D D D D MSB 8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations.
reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tPP time to determine if the data bytes have finished programming.
AT26DF081A 8.2 Sequential Program Mode The Sequential Program Mode improves throughput over the Byte/Page Program command when the Byte/Page Program command is used to program single bytes only into consecutive address locations. For example, some systems may be designed to program only a single byte of information at a time and cannot utilize a buffered Page Program operation due to design restrictions.
sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0 was currently being programmed, once the last byte of Sector 0 was programmed, the Sequential Program mode would automatically end.
AT26DF081A 8.3 Block Erase A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase.
Figure 8-5. Block Erase CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI C C C C C C MSB SO 8.4 ADDRESS BITS A23-A0 C C A A A A A A A A A A A A MSB HIGH-IMPEDANCE Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
AT26DF081A Figure 8-6. Chip Erase CS 0 1 2 3 4 5 6 7 SCK OPCODE SI C C C C C C C C MSB SO HIGH-IMPEDANCE 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command can be executed.
9.2 Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect Sector, and Write Status Register commands will not be executed. The Write Disable command is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description.
AT26DF081A program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 0 MSB SO 9.
AT26DF081A Table 9-2. WP State Valid SPRL and Global Protect/Unprotect Conditions Current SPRL Value New Write Status Register Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 0 Protection Operation New SPRL Value Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection.
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the Sector Protection Registers).
AT26DF081A Figure 9-5. Read Sector Protection Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 1 MSB 0 0 A A A A A A A A A MSB DATA BYTE SO HIGH-IMPEDANCE D MSB 9.7 D D D D D D D D D MSB Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array.
Tables 9-4 and 9-5 detail the various protection and locking states of the device. Table 9-4. Sector Protection Register States WP Sector Protection Register n(1) Sector n(1) 0 Unprotected 1 Protected X (Don't Care) Note: 1. “n” represents a sector number Table 9-5.
AT26DF081A 10. Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.
10.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be performed.
AT26DF081A 10.1.6 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset.
10.2 Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
AT26DF081A 11. Other Commands and Functions 11.1 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
Figure 11-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI SO 9Fh HIGH-IMPEDANCE Note: Each transition 11.
AT26DF081A Figure 11-2. Deep Power-down CS tEDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 1 1 0 0 1 MSB SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current 11.3 Deep Power-Down Mode Current Resume from Deep Power-down In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down command is the only command that the device will recognize while in the Deep Power-down mode.
11.4 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted.
AT26DF081A 12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature under Bias ................................. -55C to +125C *NOTICE: Storage Temperature...................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V 12.
12.4 AC Characteristics Symbol Parameter fSCK Max Units Serial Clock (SCK) Frequency 70 MHz fRDLF SCK Frequency for Read Array (Low Frequency - 03h opcode) 33 MHz tSCKH SCK High Time 6.4 ns SCK Low Time 6.4 ns SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.
AT26DF081A 12.5 Program and Erase Characteristics Symbol Parameter tPP(1) Page Program Time (256 Bytes) tBP Byte Program Time tBLKE(1) tCHPE Min Chip Erase Time (2) Write Status Register Time tWRSR Notes: Max Units 1.2 5 ms 7 Block Erase Time (2) Typ µs 4 Kbytes 50 200 32 Kbytes 250 600 64 Kbytes 400 950 6 14 sec 200 ns ms 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles. 2.
13. Waveforms Figure 13-1. Serial Input Timing tCSH CS tCSLH tSCKL tCSLS tSCKH tCSHH tCSHS SCK tDS SI SO tDH MSB LSB MSB HIGH-IMPEDANCE Figure 13-2. Serial Output Timing CS tSCKH tSCKL tDIS SCK SI tOH tV tV SO Figure 13-3.
AT26DF081A Figure 13-4. HOLD Timing – Serial Output CS SCK tHHH tHLS tHLH tHHS HOLD SI tHLQZ tHHQX SO Figure 13-5.
14. Ordering Information 14.1 Green Package Options (Pb/Halide-free/RoHS Compliant) fSCK (MHz) 70 Ordering Code Package Operation Range AT26DF081A-SSU 8S1 AT26DF081A-SU 8S2 Industrial (-40C to 85C) Package Type 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.
AT26DF081A 15. Packaging Information 15.1 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
15.2 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position.
AT26DF081A 16. Revision History Revision Level – Release Date History A – November 2005 Initial Release B – March 2006 Added Global Protect and Global Unprotect Feature - Made various minor text changes throughout document - Added Global Protect/Unprotect section to document - Changed Write Status Register section Removed EPE bit from Status Register C – April 2006 Changed Note 5 of 8S2 package drawing to generalize terminal plating comment D – May 2006 Removed “Preliminary” designation.
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