Owner's manual

1
Features
Fast Read Access Time - 120 ns
Dual Voltage Range Operation
Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V
±
10% Supply Range
Pin Compatible with JEDEC Standard AT27C4096
Low Power CMOS Operation
20 µA max. (less than 1 µA typical) Standby for V
CC
= 3.6V
36 mW max. Active at 5 MHz for V
CC
= 3.6V
JEDEC Standard Surface Mount Packages
44-Lead PLCC
40-Lead TSOP (10 x 14mm)
High Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
Rapid™ Programming algorithm - 100 µs/word (typical)
CMOS and TTL Compatible Inputs and Outputs
JEDEC Standard for LVTTL and LVBO
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
Description
The AT27BV4096 is a high performance, low power, low voltage 4,194,304-bit one-
time programmable read only memory (OTP EPROM) organized as 256K by 16 bits. It
requires only one supply in the range of 2.7V to 3.6V in normal read mode operation.
The by-16 organization makes this part ideal for portable and handheld 16 and 32 bit
microprocessor based systems using either regulated or unregulated battery power.
4-Megabit
(256K x 16)
Unregulated
Battery-Voltage
High-Speed OTP
EPROM
AT27BV4096
Rev. 0640B–10/98
Note: Both GND pins must be connected.
Pin Configurations
Pin Name Function
A0 - A17 Addresses
O0 - O15 Outputs
CE
Chip Enable
OE
Output Enable
NC No Connect
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A9
A10
A11
A12
A13
A14
A15
A16
A17
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
PLCC Top View
Note: PLCC package pins 1 and 23 are
DON’T CONNECT.
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
O13
O14
O15
CE
VPP
NC
VCC
A17
A16
A15
A14
(continued)

Summary of content (12 pages)