User Manual

1
PDIP Top View
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25
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21
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
VCC
PGM
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
VSOP Top View
Type 1
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26
25
24
23
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21
A9
A10
A11
A12
A13
A14
A15
NC
PGM
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
A2
O3
O4
O5
O6
O7
GND
Features
•
Fast Read Access Time - 45 ns
•
Low-Power CMOS Operation
– 100 µA max. Standby
– 30 mA max. Active at 5 MHz
•
JEDEC Standard Packages
– 40-Lead 600-mil PDIP
– 44-Lead PLCC
– 40-Lead VSOP (10 mm x 14 mm)
•
Direct Upgrade from 512K (AT27C516) EPROM
•
5V
±
±±
±
10% Power Supply
•
High-Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
•
Rapid™ Programming Algorithm - 100 µs/word (typical)
•
CMOS and TTL Compatible Inputs and Outputs
•
Integrated Product Identification Code
•
Commercial, Industrial and Automotive Temperature Ranges
Description
The AT27C1024 is a low-power, high-performance 1,048,576 bit one-time program-
mable read only memory (OTP EPROM) organized 64K by 16 bits. It requires only
one 5V power supply in normal read mode operation. Any word can be accessed in
less than 45 ns, eliminating the need for speed reducing WAIT states. The by-16 orga-
Rev. 0019J–07/98
AT27C1024
1-Megabit
(64K x 16)
OTP EPROM
AT27C1024
Note: Both GND pins must be connected.
Pin Configurations
Pin Name Function
A0 - A15 Addresses
O0 - O15 Outputs
CE
Chip Enable
OE Output Enable
PGM
Program Strobe
NC No Connect
(continued)
PLCC Top View
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
6 5 4 3 2 1
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
O3 O2 O1 O0
OE
NC
A0 A1 A2 A3 A4
O13 O14 O15 CE VPP NC VCC PGM NC A15 A14