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Features

•

Read Access Time - 90 ns

•

Word-wide or Byte-wide Configurable

•

8-Megabit Flash and Mask ROM Compatable

•

Low Power CMOS Operation

–100

µA Maximum Standby

– 50 mA Maximum Active at 5 MHz

•

Wide Selection of JEDEC Standard Packages

– 42-Lead 600 mil PDIP

– 44-Lead PLCC

– 44-Lead SOIC (SOP)

– 48-Lead TSOP (12 mm x 20 mm)

•

±±

10% Power Supply

•

High Reliability CMOS Technology

– 2,000 ESD Protection

– 200 mA Latchup Immunity

•

Rapid™ Programming Algorithm - 50

µs/word (typical)

•

CMOS and TTL Compatible Inputs and Outputs

•

Integrated Product Identification Code

•

Commercial and Industrial Temperature Ranges

Description

The AT27C800 is a low-power, high performance 8,388,608-bit UV erasable program-

mable read only memory (EPROM) organized as either 512K by 16 or 1024K by 8

Rev. 0801B–10/98

Pin Configurations

Pin Name Function

A0 - A18 Addresses

O0 - O15 Outputs

O15/A-1 Output/Address

BYTE

/VPP

Byte Mode/

Program Supply

CE Chip Enable

OE Output Enable

NC No Connect

TSOP

Type 1

A15

A14

A13

A12

A11

A10

A18

A17

A16

BYTE/VPP

GND

O15/A-1

O14

O13

O12

VCC

O11

O10

GND

PDIP Top View

A18

A17

GND

O10

O11

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

O15/A-1

O14

O13

O12

VCC

SOIC (SOP)

A18

A17

GND

O10

O11

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

O15/A-1

O14

O13

O12

VCC

(continued)

8-Megabit

(512K x 16 or

1024K x 8)

OTP EPROM

AT27C800

PLCC Top View

GND

A12

A13

A14

A15

A16

BYTE/VPP

GND

O15/A-1

O14

O10

O11

VCC

O12

O13

A17

A18

A10

A11

Note: PLCC Package Pin 23 is

DON’T CONNECT.

Summary of content (12 pages)

PAGE 1
Features • • • • • • • • • • • Read Access Time - 90 ns Word-wide or Byte-wide Configurable 8-Megabit Flash and Mask ROM Compatable Low Power CMOS Operation – 100 µA Maximum Standby – 50 mA Maximum Active at 5 MHz Wide Selection of JEDEC Standard Packages – 42-Lead 600 mil PDIP – 44-Lead PLCC – 44-Lead SOIC (SOP) – 48-Lead TSOP (12 mm x 20 mm) 5V ± 10% Power Supply High Reliability CMOS Technology – 2,000 ESD Protection – 200 mA Latchup Immunity Rapid™ Programming Algorithm - 50 µs/word (typical) CMOS and
PAGE 2
bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 90 ns, eliminating the need for speed-reducing WAIT states. The x16 organization makes this part ideal for high-performance 16- and 32-bit microprocessor systems. The AT27C800 can be organized as either word-wide or byte-wide. The organization is selected via the BYTE/VPP pin.
PAGE 3
AT27C800 Absolute Maximum Ratings* Temperature Under Bias ................................ -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with with Respect to Ground ..................................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground ......................................-2.0V to +14.0V(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 4
DC and AC Operating Conditions for Read Operation AT27C800 -90 -10 -12 -15 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Com. Operating Temperature (Case) Ind. VCC Power Supply DC and Operating Characteristics for Read Operation Symbol Parameter Condition ILI Input Load Current ILO IPP1(2) Max Units VIN = 0V to VCC ±1.0 µA Output Leakage Current VOUT = 0V to VCC ±5.
PAGE 5
AT27C800 Byte-Wide Read Mode AC Waveforms(1) A18 Note: 1. BYTE/VPP = VIL Byte-Wide Read Mode AC Waveforms(1) A18 Note: 1. BYTE/VPP = VIH BYTE Transition AC Waveforms A0 - A18 VALID A-1 VALID tOH tACC BYTE/VPP tST O0 - O7 DATA OUT tOH O8 - O15 DATA OUT HI-Z DATA OUT tSTD Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
PAGE 6
Input Test Waveforms and Measurement Levels Output Test Load tR, tF < 20 ns (10% to 90%) Note: CL = 100 pF including jig capacitance. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 10 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 6 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
PAGE 7
AT27C800 Programming Waveforms(1) Notes: 1. The Input Timing reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C800, a 0.1 µF capacitor is required across VPP and ground to suppress voltage transients. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.
PAGE 8
AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Limits (1) Symbol Parameter tAS Address Setup Time tOES OE Setup Time tDS Data Setup Time tAH Address Hold Time tDH Data Hold Time tDFP Input Rise and Fall Times: (10% to 90%) 20 ns Input Pulse Levels: 45V to 2.4V OE High to Output Float Delay tVPS VPP Setup Time tVCS VCC Setup Time (2) Input Pulse Levels: Input Timing Reference Level: 0.8V to 2.
PAGE 9
AT27C800 Rapid Programming Algorithm A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and BYTE/VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse.
PAGE 10
Ordering Information ICC (mA) tACC (ns) Active Standby Ordering Code Package 90 50 0.1 AT27C800-90JC AT27C800-90PC AT27C800-90RC AT27C800-90TC 44J 42P6 44R 48T Commercial (0°C to 70°C) 50 0.1 AT27C800-90JI AT27C800-90PI AT27C800-90RI AT27C800-90TI 44J 42P6 44R 48T Industrial (-40°C to 85°C) 50 0.1 AT27C800-10JC AT27C800-10PC AT27C800-10RC AT27C800-10TC 44J 42P6 44R 48T Commercial (0°C to 70°C) 50 0.
PAGE 11
AT27C800 Packaging Information 44J, 44-Lead, Plastic J Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) .045(1.14) X 45° PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .012(.305) .008(.203) .630(16.0) .590(15.0) .656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .050(1.27) TYP .500(12.7) REF SQ 42P6, 42-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) .021(.533) .013(.330) .043(1.09) .020(.508) .120(3.05) .090(2.29) .
PAGE 12
Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel U.K., Ltd.