Owner's manual

1
512K (64K x 8)
Multiplexed
Addresses/
Outputs
Low-voltage
OTP EPROM
AT27LV520
Features
8-bit Multiplexed Addresses/Outputs
Fast Read Access Time – 70 ns
Dual Voltage Range Operation
Low-voltage Power Supply Range, 3.0V to 3.6V, or
Standard 5V ± 10% Supply Range
Pin Compatible with Standard AT27C520
Low-power CMOS Operation
20 µA max. Standby for ALE = V
IH
and V
CC
= 3.6V
29 mW max. Active at 5 MHz for V
CC
= 3.6V
JEDEC Standard Packages
20-lead TSSOP
20-lead SOIC
High-reliability CMOS Technology
2,000V ESD Protection
200 mA Latch-up Immunity
Rapid
Programming Algorithm – 50 µs/Byte (Typical)
CMOS- and TTL-compatible Inputs and Outputs
JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Range
Description
The AT27LV520 is a low-power, high-performance, 524,288-bit one-time programma-
ble read-only memory (OTP EPROM) organized 64K by eight bits. It incorporates
latches for the eight lower order address bits to multiplex with the eight data bits. This
minimizes system chip count, reduces cost, and simplifies the design of multiplexed
bus systems. It requires only one power supply in the range of 3.0V to 3.6V for normal
read mode operation, making it ideal for fast, portable systems using battery power.
Any byte can be accessed in less than 70 ns.
The AT27LV520 is available in 173 mil, 20-lead TSSOP and 300 mil, 20-lead SOIC,
one-time programmable (OTP) plastic packages.
Rev. 0911D–05/00
Pin Configurations
Pin Name Function
A8 - A15 Addresses
AD0 - AD7 Addresses/Outputs
OE
/VPP Output Enable/Program Supply
ALE Address Latch Enable
TSSOP Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A10
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
A9
A8
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
AD0
(continued)
SOIC Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
VCC
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7

Summary of content (12 pages)