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Features

• Single 2.7V - 3.6V Supply

• Fast Read Access Time – 200 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

– Internal Control Timer

• Fast Write Cycle Times

– Page Write Cycle Time: 10 ms Maximum

– 1- to 64-byte Page Write Operation

• Low Power Dissipation

– 15 mA Active Current

– 20 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 10,000 Cycles

– Data Retention: 10 Years

• JEDEC Approved Byte-wide Pinout

• Commercial and Industrial Temperature Ranges

Description

The AT28BV256 is a high-performance Electrically Erasable and Programmable Read

Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access

times to 200 ns with power dissipation of just 54 mW. When the device is deselected,

the CMOS standby current is less than 200

µA.

256K (32K x 8)

Battery-Voltage

™

Parallel

EEPROMs

AT28BV256

Rev. 0273G–11/99

Pin Configurations

Pin Name Function

A0 - A14 Addresses

Chip Enable

OE Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

PDIP, SOIC

Top V i e w

A14

A12

I/O0

I/O1

I/O2

GND

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

TSOP

Top V i e w

A11

A13

VCC

A14

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

PLCC

Top View

Note: PLCC package pins 1 and 17

are DON’T CONNECT.

I/O0

A11

A10

I/O7

I/O6

I/O1

I/O2

GND

I/O3

I/O4

I/O5

A12

A14

VCC

A13

(continued)

Summary of content (12 pages)

PAGE 1
Features • Single 2.7V - 3.
PAGE 2
The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.
PAGE 3
AT28BV256 Device Operation READ: The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle.
PAGE 4
DC and AC Operating Range Com. Operating Temperature (Case) Ind. VCC Power Supply AT28BV256-20 AT28BV256-25 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C 2.7V - 3.6V 2.7V - 3.6V Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT VIL VIH VIL DIN High Z Write (2) Standby/Write Inhibit (1) VIH X X Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High Z VIL High Z Chip Erase Notes: VIL VH (3) 1. X can be VIL or VIH. 2.
PAGE 5
AT28BV256 AC Read Characteristics Symbol Parameter tACC AT28BV256-20 AT28BV256-25 Min Min Max Max Units Address to Output Delay 200 250 ns (1) CE to Output Delay 200 250 ns (2) OE to Output Delay 0 80 0 100 ns tDF(3)(4) CE or OE to Output Float 0 55 0 60 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tCE tOE 0 ns AC Read Waveforms(1)(2)(3)(4) tCE tOE tDF tOH tACC Notes: 1.
PAGE 6
AC Write Characteristics Symbol Parameter tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Note: Min (1) Time to Data Valid NR 1. NR = No Restriction.
PAGE 7
AT28BV256 Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 100 µs ns Programming Algorithm LOAD DATA AA TO ADDRESS 5555 Notes for software program code: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).
PAGE 8
DATA Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max OE to Output Delay tWR Write Recovery Time Units 0 ns 0 ns (2) tOE Notes: Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 5.
PAGE 9
AT28BV256 9
PAGE 10
Ordering Information(1) ICC (mA) tACC (ns) Active Standby Ordering Code Package Operation Range 200 15 0.02 AT28BV256-20JC AT28BV256-20PC AT28BV256-20SC AT28BV256-20TC 32J 28P6 28S 28T Commercial (0° to 70°C) 15 0.02 AT28BV256-20JI AT28BV256-20PI AT28BV256-20SI AT28BV256-20TI 32J 28P6 28S 28T Industrial (-40° to 85°C) 15 0.02 AT28BV256-25JC AT28BV256-25PC AT28BV256-20SC AT28BV256-25TC 32J 28P6 28S 28T Commercial (0° to 70°C) 15 0.
PAGE 11
AT28BV256 Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE 28P6, 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AB .045(1.14) X 45˚ PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .595(15.1) .585(14.9) .032(.813) .026(.660) .050(1.27) TYP 1.47(37.3) 1.44(36.6) .025(.635) X 30˚ - 45˚ .012(.305) .008(.203) .300(7.62) REF .430(10.9) .390(9.
PAGE 12
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