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Features

• Sensor Keys:

– Up to 11 QTouch

™

channels

• Data Acquistion:

– Measurement of keys triggered either by a signal applied to the SYNC pin or at

regular intervals timed by the AT42QT1110's internal clock

– Keys measured sequentially for better performance, or in parallel groups for faster

operation

– Raw data for key touches can be read as a report over the SPI interface

• Discrete Outputs:

– Configurable “Detect” outputs indicating individual key touch (7-key mode)

• Device Setup:

– Device configuration can be stored in EEPROM

• Technology:

– Patented spread-spectrum charge-transfer (direct mode)

• Key Outline Sizes:

– 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and

shapes possible, including solid or ring shapes

• Key Spacings:

– 7 mm center to center or more (panel thickness dependent)

• Layers Required:

–One

• Electrode Materials:

– Etched copper, silver, carbon, Indium Tin Oxide (ITO)

• Electrode Substrates:

– PCB, FPCB, plastic films, glass

• Panel Materials:

– Plastic, glass, composites, painted surfaces (low particle density metallic paints

possible)

• Panel Thickness:

– Up to 10 mm glass, 5 mm plastic (electrode size dependent)

• Key Sensitivity:

– Individually settable via simple commands over serial interface

• Adjacent Key Suppression

(AKS

™

)

– Patented AKS technology to enable accurate key detection

• Interface:

– Full-duplex SPI slave mode (1.5 MHz), “change” pin, discrete detection outputs

• Moisture Tolerance Good

• Power:

– 3V ~ 5.5V

• Package:

– 32-pin 5 x 5 mm MLF RoHS compliant

– 32-pin 7 x 7 mm TQFP RoHS compliant

• Signal Processing:

– Self-calibration, auto drift compensation, noise filtering, AKS technology

• Applications:

– Specific package qualified for automotive applications, such as radio, keyless

entry, electric windows and sat nav

QTouch

™

11-key

Sensor IC

AT42QT1110-MZ

AT42QT1110-AZ

9570H–AT42–02/10

Summary of content (48 pages)

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Features • Sensor Keys: • • • • • • • • • • • • • • • • • • • – Up to 11 QTouch™ channels Data Acquistion: – Measurement of keys triggered either by a signal applied to the SYNC pin or at regular intervals timed by the AT42QT1110's internal clock – Keys measured sequentially for better performance, or in parallel groups for faster operation – Raw data for key touches can be read as a report over the SPI interface Discrete Outputs: – Configurable “Detect” outputs indicating individual key touch (7-key m
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1. Pinout and Schematic 1.
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AT42QT1110-MZ/AT42QT1110-AZ 1.2 Pin Descriptions Table 1-1. I O Pin Listing Pin Name Type Comments If Unused, Connect To...
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1.3 Schematics Typical Circuit: 7 keys With Detect Outputs and No External Trigger Vunreg VREG QT1110 Figure 1-1.
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AT42QT1110-MZ/AT42QT1110-AZ Figure 1-2.
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Figure 1-3. Typical Circuit: 10 Keys With External Trigger (SYNC Mode) Vunreg VREG QT1110 Suggested voltage regulator manufacturers: • Torex (XC6215 series) • Seiko (S817 series) • BCDSemi (AP2121 series) Re Figure 1-1, Figure 1-2 and Figure 1-3 check the following sections for component values: • Section 3.1 on page 8: Cs capacitors (Cs0 – Cs10) • Section 3.2 on page 8: Sample resistors (Rs0 – Rs10) • Section 3.5 on page 9: Voltage levels • Section 3.
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AT42QT1110-MZ/AT42QT1110-AZ 2. Overview of the AT42QT1110 2.1 Introduction The AT42QT1110 (QT1110) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed for any touch-key applications. The keys can be constructed in different shapes and sizes. Refer to the Touch Sensors Design Guide and Application Note QTAN0002, Secrets of a Successful QTouch™ Design, for more information on construction and design methods (both downloadable from the Atmel® website).
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3. Wiring and Parts 3.1 Cs Sample Capacitors Cs0 – Cs10 are the charge sensing sample capacitors. Normally they are identical in nominal value. The optimal Cs values depend on the thickness of the panel and its dielectric constant. Thicker panels require larger values of Cs. Values can be in the range 2.2 nF (for faster operation) to 33 nF (for best sensitivity); typical values are 4.7 nF to 10 nF.
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AT42QT1110-MZ/AT42QT1110-AZ 3.5 3.5.1 Power Supply General Considerations See Section 8.2 on page 38 for the power supply range. If the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections.
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4. Detailed Operations 4.1 4.1.1 Communications Introduction All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is a synchronous serial data link that operates in full-duplex mode. The host communicates with the QT controller over the SPI using a master-slave relationship, with the QT1110 acting in slave mode. 4.1.2 SPI Operation The SPI uses four logic signals: • Serial Clock (SCK) – output from the host.
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AT42QT1110-MZ/AT42QT1110-AZ 4.1.3 CRC Bytes If enabled, a CRC checking procedure is implemented on all communications between the SPI master and the QT1110. In this case, each command or report request sent by the master must have a byte appended containing the CRC checksum of the data sent. The QT1110 will not respond to commands until the CRC byte has been received and verified. Sample C code showing the algorithm for calculating the CRC of the data can be found in Appendix A.
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Figure 4-2. Sleep Command – CRC Enabled Host (Sends on MOSI) Device (Responds on MISO) Command: 0x05 Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Command CRC: 0x3F Response: 0x3F (Expected Command CRC) When the “Send Setups” command is received, the QT1110 stops measurement of QTouch sensors and waits for 42 bytes of data to be sent. Only when all 42 bytes have been received (and the CRC byte, if CRC is enabled), the QT1110 applies all the settings to RAM and resumes measurement.
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AT42QT1110-MZ/AT42QT1110-AZ For example, Figure 4-3 on page 12 shows the exchange that takes place to read the 2-byte “All Keys” report. In this exchange, the host sends: 0xC1 — 0x00 — 0x00 and the QT1110 returns (simultaneously): 0x55 — Report Byte 0 — Report Byte 1 If CRC is enabled, this exchange is extended to 5 bytes, as shown in Figure 4-4. Figure 4-4.
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Figure 4-5. Positive Recalibration Delay Set Instruction – CRC Disabled Host (Sends on MOSI) Device (Responds on MISO) Command: 0x95 Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission “Set” Data: 0x0C Response: 0x95 (Command Just Received) With CRC Enabled, a CRC byte is also required (Figure 4-6). This is calculated for the two transmitted bytes (that is, the “Set” command and the data byte). For example, for the sequence shown in Figure 4-5 (0x95 — 0x0C), the CRC Byte is 0x9F.
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AT42QT1110-MZ/AT42QT1110-AZ 4.1.5.2 Get Instructions Get instructions are instructions that read the data from a location in the QT1110 memory map. Figure 4-7. Positive Recalibration Delay Get Instruction – CRC Disabled Host (Sends on MOSI) Device (Responds on MISO) Command: 0xD5 Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Null: 0x00 “Get” Data: 0x0C (Positive Recalibration Delay) The host sends the appropriate “Get” command, followed by a “Null” byte.
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4.1.6 4.1.6.1 Quick SPI Mode Introduction In Quick SPI Mode, the QT1110 sends a 7-byte key report at each exchange. No host commands are required over SPI in this mode; the host clocks the data bytes out in sequence. 4.1.6.2 Quick SPI Report The 7 report bytes are in the format given in Table 4-1. Table 4-1.
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AT42QT1110-MZ/AT42QT1110-AZ 4.1.6.4 Quick SPI Mode timing In Quick SPI mode, the minimum time between byte exchanges is reduced to 50 µS. If a pause in communications of 100 ms is detected during reading of the 7-byte report, the QT1110 resets the exchange, and on the next byte read it returns byte 0 of the report. 4.2 Reset The QT1110 can be reset using one of two methods: • Hardware reset: An external reset logic line can be used if desired, fed into the RESET pin.
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• Touch mode – The CHANGE pin is pulled low when one or more keys are in detect. The CHANGE pin remains low as long as there is a key in detect, regardless of communications. – The CHANGE pin is released when there are no keys in detect. No host communications are required to release the CHANGE pin. 4.6 Stand-alone Mode The QT1110 can operate in a stand-alone mode without the use of the SPI interface. The settings are loaded from EEPROM and the device operates in 7-key mode using the Detect outputs. 4.
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AT42QT1110-MZ/AT42QT1110-AZ 4.8.2 Synchronized Trigger In 11-key mode, if a time trigger is not enabled, the QT1110 operates in “synchronized” mode. In this mode, SNS10K is used as a SYNC pin to trigger key acquisition, rather than using the device’s internal clock. In this case the maximum number of keys is reduced to 10. The SYNC pin can use one of two methods to trigger key measurements, selectable via bit 4 of the Device Mode setup byte (see Section 7.4 on page 29): Low Level and Rising Edge.
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Figure 4-9. Guard Channel Example Key Pad Formed of Six Keys Guard Channel Formed of One Key 4.10 4.10.1 Self-test Functions Internal Hardware Tests Internal hardware tests check for hardware failure in the device’s internal memory areas and data paths. Any failure detected in the function or contents of application ROM, RAM or registers causes the device to reset itself. The application code is scanned with a CRC check routine to confirm that the application data is all correct.
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AT42QT1110-MZ/AT42QT1110-AZ 4.11.2 Burst Length Limitations The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of <1000 pulses. The number of pulses in the burst can be obtained by reading the key signal (that is, the number of pulses to complete measurement of the key’s signal) over the SPI interface (see Section 6.8 on page 26).
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5. Control Commands 5.1 Introduction The QT1110 control commands are those commands that affect the device operation. The control commands are listed in Table 5-1 and are described individually in the following sections. Table 5-1.
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AT42QT1110-MZ/AT42QT1110-AZ 5.4 Reset (0x04) The Reset command forces the QT1110 to reset. If the setups data is present in the EEPROM, the setups are loaded into the device. Otherwise default settings are applied. The host must wait for at least 160 ms for the operation to be completed before communications can be re-established. 5.5 Sleep (0x05) The Sleep command puts the device into sleep mode (see Section 4.3 on page 17).
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6. Report Requests 6.1 Introduction The host can request reports from the QT1110, as summarized in Table 6-1. Table 6-1.
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AT42QT1110-MZ/AT42QT1110-AZ 6.3 All Keys (0xC1) Returns a 2-byte bit-field report indicating the detection status of all 11 keys. Table 6-3. Send All Keys Report Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Byte 0 Byte 1 KEY_7 KEY_6 KEY_5 KEY_4 KEY_3 Bit 2 Bit 1 Bit 0 KEY_10 KEY_9 KEY_8 KEY_2 KEY_1 KEY_0 KEY_n: 0 = key n out of detect, 1 = key n in detect (where n is 0–10). 6.4 Device Status (0xC2) This command returns a 1-byte bit-field report indicating the overall status of the QT1110.
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6.7 Error Keys (0xC5) This command returns a 2-byte bit-field report indicating the error status of all 11 keys. Note that disabled keys do not report errors. Table 6-5. Send All Keys Report Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Byte 0 Byte 1 KEY_7 KEY_6 KEY_5 KEY_4 KEY_3 Bit 2 Bit 1 Bit 0 KEY_10 KEY_9 KEY_8 KEY_2 KEY_1 KEY_0 KEY_n: 0 = key n status good, 1 = key n in error (where n is 0–10). 6.
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AT42QT1110-MZ/AT42QT1110-AZ 6.11 Detect Output States (0xC6) This command returns a byte that indicates which PWM signal is applied to each DETECT pin. Table 6-9. Reference for Key “k” Report Format Bit 7 Byte 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DET_6 DET_5 DET_4 DET_3 DET_2 DET_1 DET_0 DET_n: 0 = “Out of Detect” PWM is output, 1 = the “In Detect” PWM is output. Note: 6.12 Note: During “LED Detect Hold Time” or “LED Fade”, the report indicates the new state of the DETECT pin.
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7. Setups and Status Information 7.1 Introduction The bytes of the setup table can be written to or read from individually. The setup table and the corresponding “Set” and “Get” commands are listed in Table 7-1. Note that there is a discontinuity in the “Set” and “Get” commands; 0xAF and 0xEF are not implemented. Table 7-1.
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AT42QT1110-MZ/AT42QT1110-AZ Table 7-1. Address 7.
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REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key acquisition. The number entered is a multiple of 16 ms. If “0” is entered, the device will operate in a continuous “free run” mode; that is, the QT1110 will not sleep after its cycle is completed but will begin the next key acquisition cycle immediately. Default KEY_AC value: Default MODE value: Default SIGNAL value: Default SYNC value: Default REPEAT_TIME value: 7.
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AT42QT1110-MZ/AT42QT1110-AZ Where data is being sent by the host, a 1-byte CRC should be sent. The QT1110 returns the expected CRC byte in the same transaction the CRC byte is sent. In this way, the host can immediately determine whether the setup data bytes were received correctly. Default GUARD_KEY value: Default GD_EN value: Default CHG value: Default CRC value: 7.6 0 (Key 0) 0 (disabled) 0 (data mode) 0 (disabled) Address 2: Detect Integrator Limit (DIL)/Drift Hold Time (DHT) Table 7-5.
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PHYST: positive hysteresis. This setting provides a greater degree of control over the implementation of the positive threshold recalibration. The positive hysteresis operates as a “modifier” for the positive threshold.
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AT42QT1110-MZ/AT42QT1110-AZ 7.10 Address 6: Lower Burst Limit (LBL) Table 7-9. Address Lower Burst Limit Bit 7 Bit 6 Bit 5 Bit 4 6 Bit 3 Bit 2 Bit 1 Bit 0 LBL Normal QTouch signals are in the range of 100 to 1000 counts for each key. The lower burst limit determines the minimum signal that is considered as a valid acquisition. If the count is lower than the lower burst limit, it is considered not to be valid and the key is set to an Error state.
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OUT_DETECTn: PWM to output when key n is “Out of Detect” (where n is 0–7). This PWM is also output if the DETECT output is “disconnected” from the key (that is, “LED_n” in address 17 is set to 0), allowing the host to directly control the PWM output. The values for the “IN_DETECTn” and “OUT_DETECTn” nibbles are listed in Table 7-12. Table 7-12. PWM Values Value Meaning 0 0% 1 12.5% 2 25% 3 37.5% 4 50% 5 62.5% 6 75% 7 87.5% 8 100% Default IN_DETECTn value: Default OUT_DETECTn value: 7.
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AT42QT1110-MZ/AT42QT1110-AZ 7.14 Address 17: LED Fade/Key to LED Table 7-14. LED Fade/Key to LED Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 17 FADE LED_6 LED_5 LED_4 LED_3 LED_2 LED_1 LED_0 FADE: enables/disables fading for all LEDs. This is a global setting; either all LEDs fade, or none of them. 0 = disable (no fade). 1 = enable fading on and off. LED_n: activates the LED output for the corresponding key output DETECTn (where n is 0–6).
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Table 7-16. Address Negative Threshold/Negative Hysteresis (Continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 25 KEY_6_NTHR KEY_6_NHSYT 26 KEY_7_NTHR KEY_7_NHSYT 27 KEY_8_NTHR KEY_8_NHSYT 28 KEY_9_NTHR KEY_9_NHSYT 29 KEY_10_NTHR KEY_10_NHSYT KEY_n_NTHR: the negative threshold for key n (where n is 0–10). The negative threshold determines how much the signal must fall (compared to the reference) before a key is considered to be “In Detect”.
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AT42QT1110-MZ/AT42QT1110-AZ 7.18 Addresses 31–41: Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Table 7-18.
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8. Specifications 8.1 Absolute Maximum Specifications Vdd -0.5 to +6V Max continuous pin current, any control or drive pin ±10 mA Voltage forced onto any pin -1.0V to (Vdd + 0.5) Volts EEPROM setups maximum writes 100,000 write cycles CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device.
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AT42QT1110-MZ/AT42QT1110-AZ 8.5 SPI Bus Specifications 8.5.1 General Specifications Parameter Specification Address space 8-bit Maximum clock rate 1.5 MHz Minimum low clock period 333 ns Minimum high clock period 333 ns Clock idle High Setup on Leading (falling) edge Clock out on Trailing (rising) edge SPI Enable delay (SS low to SCK low) 1 µs 8.5.
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Figure 8-1. Signals on SPI Pins During the Exchange of a Data Byte SCK SAMPLE MOSI/MISO CHANGE MOSI PIN CHANGE MISO PIN SS MSB 8.6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Description Operation VRST Threshold voltage low (Activate) Threshold voltage high (Release) 0.2Vdd 0.
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9570H–AT42–01/10 Note: 5.0V 3.0V Vdd (V) Note: 5.0V 7-key Parallel 7-key Serial 1010 840 815 5530 3120 2705 33.6 ms 66.4 ms 132 ms 248 ms 15.1 ms 17.2 ms 33.4 ms 65.6 ms 130 ms 244 ms 2 (32 ms Nominal) 4 (64 ms Nominal) 8 (128 ms Nominal) 15 (240 ms Nominal) 0 (Free Run) 1 (16 ms Nominal) 2 (32 ms Nominal) 4 (64 ms Nominal) 8 (128 ms Nominal) 15 (240 ms Nominal) 244 ms 132 ms 66.8 ms 34.4 ms 30.2 ms 30.2 ms 250 ms 133 ms 67.2 ms 34.4 ms 26.6 ms 26.
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8.9 8.9.1 Mechanical Dimensions AT42QT1110-MZ – 32-pin 5 x 5 mm QFN A D N J 1 0.30 DIA. TYP. LASER MARKING E SEATING PLANE C 0.080 C TOP VIEW SIDE VIEW D2 b D2/2 COMMON DIMENSIONS IN MM E2/2 SYMBOL MIN. NOM. MAX. A 0.80 0.85 0.90 J 0.00 ---- 0.05 5.00 BSC D/E D2/E2 E2 PIN1 ID 1 NOTES 3.00 3.20 3.10 N 32 e 0.50 BSC L 0.35 0.40 0.45 b 0.18 0.25 0.30 L N See Options A, B, C BOTTOM VIEW Option B Option A e 1 1 1 N Pin 1# Chamfer (C 0.
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AT42QT1110-MZ/AT42QT1110-AZ 8.9.2 AT42QT1110-AZ – 32-pin 7 x 7 mm TQFP SYMBOL R Atmel Nantes S.A. La Chantrerie - BP 70602 44306 Nantes Cedex 3 - France TITLE NOTE DRAWING NO. REV.
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8.10 8.10.1 Marking AT42QT1110-MZ – 32-pin 5 x 5 mm QFN Pin 1 ID 32 1 ATMEL QT1110 MZ 4R4 Date code Country Code Abbreviation of Part Number: AT42QT1110 - MZ Datecode/ Lot Number Code Revision: 4.4, Released Lot number 8.10.2 AT42QT1110-AZ – 32-pin 7 x 7 mm TQFP 32 Pin 1 ID 1 Abbreviation of Part Number: AT42QT1110 - AZ ATMEL QT1110AZ44 Code Revision: 4.
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AT42QT1110-MZ/AT42QT1110-AZ 8.11 Part Number Part Number 8.
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Appendix A. CRC Calculation If the use of a cyclic redundancy check (CRC) during data transmission is enabled, the host must generate a valid CRC so that this can be correctly compared to the corresponding CRC generated by the QT1110. This appendix gives example C code to show how the CRC can be generated by the host.
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AT42QT1110-MZ/AT42QT1110-AZ Revision History Revision No. History Revision A – November 2008  Initial Release Revision B – December 2008  Updated for chip revision 2.1 Revision C – December 2008  Updated SPI specifications Revision D – February 2009  Updated for chip revision 3.1  Updated for chip revision 3.2: added self-test function  Updated for chip revision 4.3: added Quick SPI mode   Updated specifications Erratum note added concerning CRC calculations for chip revision 4.
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 01-05 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.