Features • • • • • • • • • • • • • Single 2.7V - 3.
layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB011B does not require high input voltages for programming.
AT45DB011B Memory Architecture Diagram BLOCK ARCHITECTURE SECTOR ARCHITECTURE SECTOR 0 = 2112 BYTES (2K + 64) SECTOR 0 BLOCK 0 PAGE ARCHITECTURE PAGE 0 8 Pages PAGE 1 BLOCK 2 SECTOR 1 = 65,472 BYTES (62K + 1984) SECTOR 1 BLOCK 3 BLOCK 0 BLOCK 1 PAGE 6 PAGE 7 PAGE 8 BLOCK 29 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 34 PAGE 9 BLOCK 1 BLOCK 30 PAGE 14 PAGE 15 PAGE 16 SECTOR 2 SECTOR 2 = 67,584 BYTES (64K + 2K) PAGE 17 PAGE 18 BLOCK 61 PAGE 509 BLOCK 62 PAGE 510 BLOCK 63 PAGE 511 Block = 2112
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided.
AT45DB011B STATUS REGISTER READ: The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of the buffer. An 8-bit opcode of 88H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify the page in the main memory to be written, and nine additional don’t care bits. When a low-tohigh transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory.
AT45DB011B MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first shifted into the buffer from the SI pin and then programmed into a specified page in the main memory. An 8-bit opcode of 82H is followed by the six reserved bits and 18 address bits.
Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AT45DB011B Operation Mode Summary The modes described can be separated into two groups – modes which make use of the Flash memory array (Group A) and modes which do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Main Memory Page to Buffer Transfer 3. Main Memory Page to Buffer Compare 4. Buffer to Main Memory Page Program with Built-in Erase 5. Buffer to Main Memory Page Program without Built-in Erase 6. Page Erase 7. Block Erase 8.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences.
AT45DB011B Table 1. Read Commands Command SCK Mode Opcode Inactive Clock Polarity Low or High 68H SPI Mode 0 or 3 E8H Inactive Clock Polarity Low or High 52H SPI Mode 0 or 3 D2H Inactive Clock Polarity Low or High 54H SPI Mode 0 or 3 D4H Inactive Clock Polarity Low or High 57H SPI Mode 0 or 3 D7H Continuous Array Read Main Memory Page Read Buffer Read Status Register Read Table 2.
Table 4.
AT45DB011B DC Characteristics Symbol Parameter Condition ISB Standby Current ICC1(1) Typ Max Units CS, RESET, WP = VIH, all inputs at CMOS levels 2 10 µA Active Current, Read Operation f = 20 MHz; IOUT = 0 mA; VCC = 3.6V 4 10 mA ICC2 Active Current, Program/Erase Operation VCC = 3.6V 10 25 mA ILI Input Load Current VIN = CMOS levels 1 µA ILO Output Leakage Current VI/O = CMOS levels 1 µA VIL Input Low Voltage 0.
Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 2.0 0.8 0.45V AC MEASUREMENT LEVEL tR, tF < 3 ns (10% to 90%) Output Test Load DEVICE UNDER TEST 30 pF AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams.
AT45DB011B Reset Timing (Inactive Clock Polarity Low Shown) CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. Command Sequence for Read/Write Operations (Except Status Register Read) SI MSB r r r r CMD r r XX Reserved for larger densities Notes: 8 bits 8 bits XXXX XXXX Page Address (PA8-PA0) 8 bits XXXX XXXX LSB Byte/Buffer Address (BA8-BA0/BFA8-BFA0) 1.
Write Operations The following block diagram and waveforms illustrate the various write sequences available.
AT45DB011B Read Operations The following block diagram and waveforms illustrate the various read sequences available.
Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 0 1 X X 65 66 67 68 tSU SI tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 2111 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 0 1 0 1 tV SO 18 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 AT45DB011B 1984E–DFLSH–10/02
AT45DB011B Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Buffer Read (Opcode: 54H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 42 43 tSU COMMAND OPCODE SI 1 0 1 0 tV HIGH-IMPEDANCE SO DATA OUT D7 MSB D6 D5 Status Register Read (Opcode: 57H) CS SCK 1 2 0 1 3 4 5 6 7 8 1 1 9 10 11 12 16 17 tSU COMMAND OPCODE SI 0 1 0 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D1 D0 LSB D7 MSB 19 1984E–DFLSH–10/02
Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 0 X X X tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 2111 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 67 68 tSU COMMAND OPCODE SI 0 1 0 1 0 X X X X X tV SO 20 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 D4 AT45DB011B 1984E–DFLSH–10/02
AT45DB011B Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Buffer Read (Opcode: 54H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH-IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: 57H) CS SCK 1 2 3 4 5 6 7 8 9 10 11 12 17 18 tSU COMMAND OPCODE SI 0 1 0 1 0 1 1 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D4 D0 LSB D7 MSB D6 21 1984E–DFLSH
Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 62 63 64 1 1 X X X 65 66 67 tSU SI tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 2111 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 1 1 0 1 tV SO 22 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 D4 AT45DB011B 1984E–DFLSH–10/02
AT45DB011B Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Buffer Read (Opcode: D4H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 42 43 tSU COMMAND OPCODE SI 1 1 1 0 tV DATA OUT HIGH-IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: D7H) CS SCK 1 2 1 1 3 4 5 6 7 8 1 1 9 10 D7 MSB D6 11 12 16 17 tSU COMMAND OPCODE SI 0 1 0 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D5 D4 D1 D0 LSB D7 MSB 23 1984E–DFLSH–10/02
Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 1 X X X tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 2111 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 67 68 tSU COMMAND OPCODE SI 1 1 0 1 0 X X X X X tV SO 24 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 D4 AT45DB011B 1984E–DFLSH–10/02
AT45DB011B Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Buffer Read (Opcode: D4H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 1 1 0 0 X X X X X tV DATA OUT HIGH-IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: D7H) CS SCK 1 2 3 4 5 6 7 8 9 10 11 12 17 18 tSU COMMAND OPCODE SI 1 1 0 1 0 1 1 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D4 D0 LSB D7 MSB D6 25 1984E–DFLSH–10/02
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array START provide address and data BUFFER WRITE (84H) MAIN MEMORY PAGE PROGRAM (82H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H) END Notes: 26 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
AT45DB011B Figure 2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE to BUFFER TRANSFER (53H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H) MAIN MEMORY PAGE PROGRAM (82H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H) (2) Auto Page Rewrite (58H) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
Ordering Information ICC (mA) fSCK (MHz) Active Standby 20 10 20 10 Ordering Code Package Operation Range 0.01 AT45DB011B-CC AT45DB011B-SC AT45DB011B-XC 9C1 8S2 14X Commercial (0°C to 70°C) 0.01 AT45DB011B-CI AT45DB011B-SI AT45DB011B-XI 9C1 8S2 14X Industrial (-40°C to 85°C) Package Type 9C1 9-ball (3 x 3 Array), 1.0 mm Pitch, 5 x 5 mm Plastic Chip-scale Ball Grid Array Package (CBGA) 8S2 8-lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 14X 14-lead, 0.
AT45DB011B Packaging Information 9C1 – CBGA Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 5.10(0.201) 4.90(0.193) A1 ID 5.10(0.201) 4.90(0.193) SIDE VIEW TOP VIEW 0.25(0.010)MIN 1.20(0.047)MAX 2.0 (0.079) 1.50(0.059) REF 3 2 1 1.50(0.059) REF A B 1.00 (0.0394) BSC NON-ACCUMULATIVE 2.0 (0.079) C 0.40 (0.016) DIA BALL TYP 1.00 (0.
8S2 – EIAJ SOIC 1 H N Top View e b A D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL C A1 L E End View NOM MAX NOTE A 1.78 2.03 A1 0.05 0.33 b 0.35 0.51 5 C 0.18 0.25 5 D 5.13 5.38 E 5.13 5.41 H 7.62 8.38 L 0.51 e Notes: 1. 2. 3. 4. 5. MIN 2, 3 0.89 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included.
AT45DB011B 14X – TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 5.10 (0.201) 4.90 (0.193) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º~ 8º 0.75 (0.030) 0.45 (0.018) 05/16/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 14X (Formerly "14T"), 14-lead (4.
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