Features • Single 2.7V to 3.
The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. To allow for simple in-system reprogrammability, the AT45DB011D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations.
AT45DB011D Figure 2-1. SOIC Top View SI SCK RESET CS Note: 1 2 3 4 Figure 2-2. 8 7 6 5 UDFN Top View(1) SI SCK RESET CS SO GND VCC WP SO GND 6 VCC 5 WP 1 8 2 7 3 4 1. The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GND. 3.
. Memory Array To provide optimal flexibility, the memory array of the AT45DB011D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block or page level.
AT45DB011D 6. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the SRAM data buffer. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode. 6.
(A16 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data.
AT45DB011D operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).
bytes), the opcode 83H must be clocked into the device followed by three address bytes consisting of seven don’t care bits, nine page address bits (A16 - A8) that specify the page in the main memory to be written and eight don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory.
AT45DB011D Table 7-1. Block Erase Addressing PA8/ A16 PA7/ A15 PA6/ A14 PA5/ A13 PA4/ A12 PA3/ A11 PA2/ A10 PA1/ A9 PA0/ A8 Block 0 0 0 0 0 0 X X X 0 0 0 0 0 0 1 X X X 1 0 0 0 0 1 0 X X X 2 0 0 0 0 1 1 X X X 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 1 1 1 0 0 X X X 60 1 1 1 1 0 1 X X X 61 1 1 1 1 1 0 X X X 62 1 1 1 1 1 1 X X X 63 7.
7.7 Chip Erase The entire main memory can be erased at one time by using the Chip Erase command. To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deasserted to start the erase process.
AT45DB011D 8. Sector Protection Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin.
Figure 8-2. Disable Sector Protection CS Opcode Byte 1 SI Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Each transition represents 8 bits 8.1.3 Various Aspects About Software Controlled Protection Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host processor.
AT45DB011D Table 9-1. Time Period WP Pin Enable Sector Protection Command Disable Sector Protection Command Sector Protection Status Sector Protection Register X Issue Command – Disabled Disabled Enabled Read/Write Read/Write Read/Write 1 High Command Not Issued Previously – Issue Command 2 Low X X Enabled Read Only High Command Issued During Period 1 or 2 – Issue Command Not Issued Yet Issue Command – Enabled Disabled Enabled Read/Write Read/Write Read/Write 3 9.
9.1.1 Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin.
AT45DB011D 9.1.2 Program Sector Protection Register Command Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command. To program the Sector Protection Register, the CS pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and FCH.
9.1.3 Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and three dummy bytes must be clocked in via the SI pin. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pins will result in data for the content of the Sector Protection Register being output on the SO pin.
AT45DB011D 10. Security Features 10.1 Sector Lockdown The device incorporates a Sector Lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.
10.1.1 Sector Lockdown Register Sector Lockdown Register is a nonvolatile register that contains 4-bytes of data, as shown below: Table 10-2. Sector Lockdown Register Sector Number 0 (0a, 0b) 1 to 3 Locked FFH See Below Unlocked 00H Table 10-3. 10.1.
AT45DB011D 10.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128bytes that is divided into two portions. The first 64-bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64-bytes have been programmed, they cannot be reprogrammed.
10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, the content of the Security Register can be clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.
AT45DB011D 11.3 Auto Page Rewrite This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to the buffer and then the same data (from the buffer) is programmed back into its original page of main memory.
the data in the buffer. If bit six is a one, then at least one bit of the data in the main memory page does not match the data in the buffer. Bit one in the Status Register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-controlled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled.
AT45DB011D 12.1 Resume from Deep Power-down The Resume from Deep Power-down command takes the device out of the Deep Power-down mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the CS pin must first be asserted and an opcode of ABH command must be clocked in via input pin (SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to terminate the Deep Power-down mode.
13.1 Programming the Configuration Register To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H.
AT45DB011D 14.1 14.1.1 Manufacturer and Device ID Information Byte 1 – Manufacturer ID JEDEC Assigned Code Hex Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1FH 0 0 0 1 1 1 1 1 14.1.2 Manufacturer ID Byte 2 – Device ID (Part 1) Family Code Density Code Hex Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 22H 0 0 1 0 0 0 1 0 Density Code 14.1.
14.2 Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. 2. 3. 4. 5. Main Memory Page Read Continuous Array Read Read Sector Protection Register Read Sector Lockdown Register Read Security Register Group B commands consist of: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
AT45DB011D 15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2H Continuous Array Read (Legacy Command) E8H Continuous Array Read (Low Frequency) 03H Continuous Array Read (High Frequency) 0BH Buffer Read (Low Frequency) D1H Buffer Read D4H Table 15-2.
Table 15-4. Additional Commands Command Main Memory Page to Buffer Transfer 53H Main Memory Page to Buffer Compare 60H Auto Page Rewrite through Buffer 58H Deep Power-down B9H Resume from Deep Power-down ABH Status Register Read D7H Manufacturer and Device ID Read 9FH Table 15-5. Legacy Commands(1) Command Opcode Buffer Read 54H Main Memory Page Read 52H Continuous Array Read 68H Status Register Read 57H Note: 28 Opcode 1.
AT45DB011D Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes) 0 53h 0 1 0 1 0 0 1 58h 0 1 0 1 1 0 0 60h 0 1 1 0 0 0 77h 0 1 1 1 0 1 x x x x A x x x x A x x x x x A x x x x x A x x x x A0 x 1 0 A1 x x 1 0 A2 x x 0 0 A3 x x 1 1 A4 x x 0 0 A A5 x 1 0 1 x A6 0 1 0 0 x A7 0 0 50h x A8 x 0Bh x A9 x x 1 A10 x 0 1 A11 1 0 A A A A A A A A A x Additional Don’t Care Bytes A12
Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264-Bytes) BA0 x x x x P P P P P P P P P B B B B B B B B B N/A 0Bh 0 0 0 0 1 0 1 1 x x x 50h 0 1 0 1 0 0 0 0 x x x x x x P P P P P P P P P B B B B B B B B B 1 x x x P P P P P x x x x x x x x x x N/A 53h 0 1 0 1 0 0 1 1 x x 58h 0 1 0 1 1 0 0 0 x x x x x x P P P P P P P P P x x x x x x x x x N/A x x x x P P P P P P P P P x x x
AT45DB011D 16. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
18. Electrical Specifications Table 18-1. Absolute Maximum Ratings* Temperature under Bias ................................. -55C to +125C *NOTICE: Storage Temperature...................................... -65C to +150C All Input Voltages (except VCC but including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Table 18-2.
AT45DB011D Table 18-4. AC Characteristics – RapidS/Serial Interface Symbol Parameter fSCK Max Units SCK Frequency 66 MHz fCAR1 SCK Frequency for Continuous Array Read 66 MHz fCAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 MHz tWH SCK High Time 6.8 ns SCK Low Time 6.8 ns SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.
19. Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 1.5V 0.45V AC MEASUREMENT LEVEL tR, tF < 2ns (10% to 90%) 20. Output Test Load DEVICE UNDER TEST 30pF 21. AC Waveforms Six different timing waveforms are shown on page 35. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition.
AT45DB011D 21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU tH VALID IN SI 21.2 tDIS HIGH IMPEDANCE Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO tHO HIGH Z VALID OUT tSU tH VALID IN SI 21.3 tDIS HIGH IMPEDANCE Waveform 3 – RapidS Mode 0 (FMAX = 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU SI 21.
21.5 Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
AT45DB011D 21.6 Reset Timing CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE SO (OUTPUT) HIGH IMPEDANCE SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted 21.7 Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB CMD XXXXXXX 7 Don’t Care Bits 21.
22. Write Operations The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY PAGE (256-/264 BYTES) BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (256-/264-BYTES) BUFFER WRITE I/O INTERFACE SI 22.1 Buffer Write Completes writing into the buffer CS BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 SI (INPUT) 22.
AT45DB011D 23. Read Operations The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY PAGE (256-/264-BYTES) MAIN MEMORY PAGE TO BUFFER BUFFER (256-/264-BYTES) BUFFER READ MAIN MEMORY PAGE READ I/O INTERFACE SO 23.1 Main Memory Page Read CS ADDRESS FOR BINARY PAGE SIZE A16 A15-A8 A7-A0 SI (INPUT) CMD PA8-7 PA6-0, BA8 BA7-0 X X 4 Dummy Bytes SO (OUTPUT) 23.
23.3 Buffer Read CS BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 1 Dummy Byte SI (INPUT) CMD X X BFA7- 0 X..X, BFA8 SO (OUTPUT) n n+1 Each transition represents 8 bits 24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3 24.
AT45DB011D 24.3 Continuous Array Read (Low Frequency: Opcode 03H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A16-A0 0 1 1 MSB A A A A A A A A A MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB 24.
24.6 Buffer Read (Low Frequency: Opcode D1H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 OPCODE SI 1 1 0 1 0 0 0 1 MSB X X X X X X A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB 24.
AT45DB011D 24.9 Read Security Register (Opcode 77H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 1 1 1 0 DON'T CARE 1 1 1 MSB X X X X X X X X X MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB D MSB 24.
25. Auto Page Rewrite Flowchart Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
AT45DB011D Figure 25-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H) AUTO PAGE REWRITE (58H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
26. Ordering Information 26.1 Ordering Code Detail AT 4 5 DB 0 1 1 D – SSH – B Designator Shipping Carrier Option B = Bulk (tubes) Y = Trays T = Tape and reel Product Family Device Grade H = NiPdAu lead finish, industrial temperature range (-40°C to +85°C) Package Option Device Density SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.208" wide SOIC M = 8-pad, 5 x 6 x 0.6mm UDFN 01 = 1-megabit Interface 1 = Serial Device Revision 26.
AT45DB011D 27. Packaging Information 27.1 8MA1 – UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A E2 K 0.45 8 Pin #1 Notch (0.20 R) (Option B) 7 Option A Pin #1 Chamfer (C 0.35) 1 2 e D2 6 3 5 4 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C b BOTTOM VIEW L NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.
27.2 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
AT45DB011D 27.3 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW MAX NOM NOTE A 1.70 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° e Notes: 1. 2. 3. 4. MIN 2.16 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
28. Revision History 50 Revision Level – Release Date History A – June 2006 Initial Release B – February 2007 Removed RDY/BUSY pin references. C – November 2007 Fixed the typographical error in the Block Architecture diagram. Changed tVCSL time to 1ms. Changed IDP (Max) to 15µA. Added Chip Erase time. Changed tRDPD time to 35µs. Changed the tXFR and tCOMP times from 400µs to 200µs. Changed part number ordering code to reflect NiPdAu lead finish. - Changed AT45DB011D-SSU to AT45DB011D-SSH.
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