Features • Single 2.7V to 3.
The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. To allow for simple in-system reprogrammability, the AT45DB021D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations.
AT45DB021D Figure 1-1. SOIC Top View SI SCK RESET CS Notes: 1 2 3 4 Figure 1-2. 8 7 6 5 UDFN Top View(1) SI SCK RESET CS SO GND VCC WP SO GND 6 VCC 5 WP 1 8 2 7 3 4 1. The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GND Figure 1-3.
2. Memory Array To provide optimal flexibility, the memory array of the AT45DB021D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block or page level.
AT45DB021D 4. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the SRAM data buffer. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode. 4.
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data buffer and leaves the contents of the buffer unchanged. 4.
AT45DB021D read data from the buffer. The D4H opcode can be used at any SCK frequency up to the maximum specified by fCAR1. The D1H opcode can be used for lower frequency read operations up to the maximum specified by fCAR2. To perform a buffer read from the DataFlash standard buffer (264-bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8 - BFA0).
5.4 Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (264-bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of five don’t care bits, 10 page address bits (PA9 - PA0) that specify the page in the main memory to be erased and nine don’t care bits.
AT45DB021D the binary page size (25-bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of six don’t care bits and seven page address bits (A17 - A11) and 11 don’t care bits. To perform a sector 1-seven erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of six don’t care bit and three page address bits (A17 - A15) and 16 don’t care bits.
5.8 Main Memory Page Program Through Buffer This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into the buffer from the input pin (SI) and then programmed into a specified page in the main memory. To perform a main memory page program through buffer for the DataFlash standard page size (264-bytes), a 1-byte opcode, 82H, must first be clocked into the device, followed by three address bytes.
AT45DB021D 6.1.2 Disable Sector Protection Command To disable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be disabled.
The table below details the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command. WP Pin and Protection Status Figure 7-1. 1 3 2 WP Table 7-1.
AT45DB021D 7.1.1 Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin.
guaranteed. Furthermore, if more than 8-bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if 9-bytes of data are clocked in, then the ninth byte will be stored at byte location zero of the Sector Protection Register. If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to that byte location cannot be guaranteed.
AT45DB021D 7.1.4 Various Aspects About the Sector Protection Register The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully evaluate the number of times the Sector Protection Register will be modified during the course of the applications’ life cycle.
8.1.1 Sector Lockdown Register Sector Lockdown Register is a nonvolatile register that contains 8-bytes of data, as shown below: Table 8-2. Sector Lockdown Register Sector Number 0 (0a, 0b) 1 to 7 Locked FFH See Below Unlocked Table 8-3. 8.1.
AT45DB021D 8.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128-bytes that is divided into two portions. The first 64-bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64-bytes have been programmed, they cannot be reprogrammed.
8.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, the content of the Security Register can be clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.
AT45DB021D Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to the buffer and then the same data (from the buffer) is programmed back into its original page of main memory.
Table 9-1. 10. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDY/BUSY COMP 0 1 0 1 PROTECT PAGE SIZE Deep Power-down After initial power-up, the device will default in standby mode. The Deep Power-down command allows the device to enter into the lowest power consumption mode. To enter the Deep Power-down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of B9H command must be clocked in via input pin (SI).
AT45DB021D 11. “Power of 2” Binary Page Size Option “Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size (256-bytes) or the DataFlash standard page size (264-bytes). The “power of 2” page size is a One-time Programmable (OTP) register and once the device is configured for “power of 2” page size, it cannot be reconfigured again.
two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state.
AT45DB021D 12.2 Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. 2. 3. 4. 5. Main Memory Page Read Continuous Array Read Read Sector Protection Register Read Sector Lockdown Register Read Security Register Group B commands consist of: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
13. Command Tables Table 13-1. Read Commands Command Opcode Main Memory Page Read D2H Continuous Array Read (Legacy Command) E8H Continuous Array Read (Low Frequency) 03H Continuous Array Read (High Frequency) 0BH Buffer Read (Low Frequency) D1H Buffer Read D4H Table 13-2.
AT45DB021D Table 13-4. Additional Commands Command Opcode Main Memory Page to Buffer Transfer 53H Main Memory Page to Buffer Compare 60H Auto Page Rewrite through Buffer 58H Deep Power-down B9H Resume from Deep Power-down ABH Status Register Read D7H Manufacturer and Device ID Read 9FH Table 13-5. Legacy Commands(1) Command Opcode Buffer Read 54H Main Memory Page Read 52H Continuous Array Read 68H Status Register Read 57H Note: 1.
Table 13-6.
AT45DB021D Table 13-7.
14. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 14.
AT45DB021D read operations after reprogramming before the contents could potentially be altered. For example, if the Serial Flash is being used for boot code storage, then it would take 800,000,000 boot operations before that boot code may become altered, provided that the boot code was not updated or reprogrammed. If an application was to read the entire memory array non-stop at a clock frequency of 10MHz, it would take over five years to reach 800,000,000 read operations.
Table 16-2. DC Characteristics Symbol Parameter Condition IDP Deep Power-down Current ISB Standby Current ICC1 (1) Active Current, Read Operation Min Typ Max Units CS, RESET, WP = VIH, all inputs at CMOS levels 15 25 µA CS, RESET, WP = VIH, all inputs at CMOS levels 25 50 µA f = 20MHz; IOUT = 0mA; VCC = 3.6V 7 10 mA f = 33MHz; IOUT = 0mA; VCC = 3.6V 8 12 mA f = 50MHz; IOUT = 0mA; VCC = 3.6V 10 14 mA f = 66MHz; IOUT = 0mA; VCC = 3.
AT45DB021D Table 16-3. AC Characteristics – RapidS/Serial Interface Symbol Parameter fSCK Min Typ Max Units SCK Frequency 66 MHz fCAR1 SCK Frequency for Continuous Array Read 66 MHz fCAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 MHz tWH SCK High Time 6.8 ns SCK Low Time 6.8 ns (1) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF (1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.
Figure 16-2. Output Test Load DEVICE UNDER TEST 30pF 17. AC Waveforms Six different timing waveforms are shown on page 32. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 66MHz.
AT45DB021D Figure 17-3. Waveform 3 – RapidS Mode 0 (FMAX = 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU SI tDIS HIGH IMPEDANCE tH VALID IN Figure 17-4. Waveform 4 – RapidS Mode 3 (FMAX = 66MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO HIGH Z tHO VALID OUT tSU SI 17.
Figure 17-5. RapidS Mode Slave CS 1 8 2 3 4 5 6 1 8 7 2 3 4 5 6 1 7 SCK B E A MOSI C D MSB LSB BYTE-MOSI H G I F MISO MSB LSB BYTE-SO MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master is the host controller and the Slave is the DataFlash The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
AT45DB021D Figure 17-8. Command Sequence for Read/Write Operations for Page Size 264-Bytes (Except Status Register Read, Manufacturer and Device ID Read) CMD SI (INPUT) MSB 8-bits 8-bits XXXXX 8-bits XXXX XXXX XXXX XXXX XX X 5 Don’t Care Bits Page Address (PA9 - PA0) LSB Byte/Buffer Address (BA8 - BA0/BFA8 - BFA0) Figure 17-9.
Figure 17-11. Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page) Starts self-timed erase/program operation CS BINARY PAGE SIZE A17-A8 + 8 DON'T CARE BITS SI (INPUT) CMD PA9-7 PA6-0, X XXXX XX Each transition represents 8 bits 18. n = 1st byte read n+1 = 2nd byte read Read Operations The following block diagram and waveforms illustrate the various read sequences available.
AT45DB021D Figure 18-2. Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer) Starts reading page data into buffer CS BINARY PAGE SIZE 6 DON’T CARE BITS + A17-A8 + 8 DON'T CARE BITS SI (INPUT) CMD X···X, PA9-7 XXXX XXXX PA6-0, X SO (OUTPUT) Figure 18-3. Buffer Read CS BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 1 Dummy Byte SI (INPUT) CMD X X BFA7- 0 X..X, BFA8 SO (OUTPUT) n n+1 Each transition represents 8 bits 19.
Figure 19-2. Continuous Array Read (Opcode 0BH) CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 SCK OPCODE SI 0 0 0 0 1 ADDRESS BITS A17 - A0 0 1 1 MSB A A A A A A A DON'T CARE A A MSB X X X X X X X X MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB D D MSB Figure 19-3.
AT45DB021D Figure 19-5. Buffer Read (Opcode D4H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 OPCODE SI 1 1 0 1 0 1 0 0 MSB X X X X X X A A A MSB DON'T CARE X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D MSB D D D D D D D MSB Figure 19-6.
Figure 19-8. Read Sector Lockdown Register (Opcode 35H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 1 1 0 DON'T CARE 1 0 1 MSB X X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB D MSB Figure 19-9.
AT45DB021D Figure 19-11. Manufacturer and Device Read (Opcode 9FH) CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI 9FH HIGH-IMPEDANCE SO Note: Each transition 20. 1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 00H shown for SI and SO represents one byte (8 bits) Auto Page Rewrite Flowchart Figure 20-1.
Figure 20-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H) AUTO PAGE REWRITE (58H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
AT45DB021D 21. Ordering Information 21.1 Ordering Code Detail AT 4 5 DB 0 2 1 D – SSH – B Designator Shipping Carrier Option B = Bulk (tubes) Y = Trays T = Tape and reel Product Family Device Grade H = NiPdAu lead finish, industrial temperature range (-40°C to +85°C) Package Option Device Density M = 8-lead, 6 x 5 x 0.6mm UDFN SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.209" wide SOIC 02 = 2-megabit Interface 1 = Serial Device Revision 21.
22. Packaging Information 22.1 8MA1 – UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A E2 K 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 2 e D2 6 3 5 4 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C b L BOTTOM VIEW NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.
AT45DB021D 22.2 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
22.3 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW 2.16 A1 0.05 0.25 NOTE b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position.
AT45DB021D 23. Revision History Doc. Rev. Date Comments A 06/2006 Initial release. B 02/2007 Removed RDY/BUSY pin references.
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